Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Karen Linser, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Oct 25, 2011

Learn how StarRC new custom design features including 3D symmetric net extraction, optimized PCELL solution, and qualified PDK support, enable accurate and productive analog/mixed-signal design.
Krishnakumar Sundaresan, Principal Engineer/Manager, CAE, Synopsys
Oct 20, 2011

See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011

Learn how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for quality assurance.
Richard Bishop, Member of Technical Staff, AMD; Karen Linser, Senor Corporate Applications Engineer, Implementation Group, Synopsys
May 18, 2011

Learn the details of the faster multicore architecture, and the techniques to achieve best correlation between hierarchical and full-chip flat extraction.
Krishnakumar Sundaresan, Principal Engineer/CAE Manager, StarRC, Synopsys; Beifang Qiu, Senior R&D Manager, StarRC, Synopsys
Apr 26, 2011

Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Philip Cuney, Design Support Technical Leader, Design Support & Methodology Group, Home Entertainment & Displays, ST Microelectronics
Apr 20, 2011

Learn how the advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins.
Chirag Patel, Staff Engineer, CAE, Synopsys; Peter O’Brien, Senior Staff R&D Engineer, Synopsys
Apr 13, 2011

Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies.
Willy Chen, Program Manager, Design Methodology Division, TSMC; Norb Heindl, Senior Staff Engineer CAE, Implementation Group, Synopsys
Feb 23, 2011

Increasing design complexity and the impact of new parasitic effects make accuracy and productivity for IC design and signoff analysis even more challenging beyond the 28nm process node. In this webinar, Synopsys experts will discuss how StarRC addresses these advanced challenges at 28nm through silicon-accurate modeling and high-performance extraction, enabling SoC designers to achieve signoff with increased confidence.
Krishnakumar Sundaresan, CAE, Synopsys
Sep 14, 2010

This technical webinar will explain how PrimeTime PX can be used to analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating. Attendees will learn how to further optimize their designs for power by analyzing which low-power techniques work best under differing conditions. You will also learn how to use PrimeTime PX to understand which modes of operation consume the most power.
David Le, Senior Manager, CAE, Implementation Group, Synopsys; Maria Tovey, Staff Engineer, CAE, Implementation Group, Synopsys
Aug 03, 2010

This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010

How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.
Uyen Tran, Director CAE, Synopsys; Norb Heindl, Senior Staff Engineer, CAE, Synopsys
Feb 17, 2010

A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Synopsys; Troy Epperly, Corporate Applications Engineer, Synopsys
Jan 20, 2010

Join our experts to learn how you can use In-Design Rail Analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
Tom Chau, Group CAE Director, Synopsys; Dr. Henry Sheng, R&D Group Director, Synopsys
Jun 25, 2009