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Enabling 20nm Design: A Foundry and EDA Perspective
TSMC and Synopsys will jointly present some of the key design and manufacturing challenges at 20nm process technology. They will highlight the need for early collaboration between EDA, customers and the foundry to ensure a smooth path to tape-out and first-time silicon success.
Willy Chen, Department Manager, Design Methodology & Service Marketing Program R&D, TSMC; Dr. Tong Gao, Synopsys Fellow, Synopsys
May 01, 2012 | | | Efficient Clock Distribution: A Critical Factor in Design Performance
Synopsys and LSI jointly present on designing today’s high frequency, low power clocks. LSI will present their perspective on the challenges of clock distribution and Synopsys will focus on the solutions that enable designers to achieve the best QoR and lowest power at today’s advanced technology nodes.
JC Parker, Senior Director of Design Tools and Methodologies, LSI; Dennis Ding, R&D Director, Synopsys
Apr 04, 2012 | | | Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012 | | | Addressing Challenges at 20nm: A Foundry and EDA perspective
Synopsys and Samsung jointly present some of the key challenges of designing and manufacturing at 20nm. Learn about solutions that address these challenges.
KK Lin, Director, Foundry Design Enablement, Samsung; Tong Gao, R&D Fellow, Synopsys
Oct 24, 2011 | | | Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle
Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011 | | | Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011 | | | Optimize in Less Time: Rapid Design Exploration with Lynx Design System
Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.
Aditya Ramachandran, CAE, Lynx Design System, Synopsys
Jul 19, 2011 | | | Faster ECO Fixing Flows with PrimeTime and IC Compiler
This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010 | | | IC Compiler Ecosystem
There is a thriving ecosystem around IC Compiler and the Galaxy Implementation Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity.
JC Lin, Synopsys
Oct 31, 2009 | | | Faster Power/Ground Grid Closure with In-Design Rail Analysis
Join our experts to learn how you can use In-Design Rail Analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
Tom Chau, Group CAE Director, Synopsys; Dr. Henry Sheng, R&D Group Director, Synopsys
Jun 25, 2009 | | | Faster Design Closure with Congestion Minimization
This webinar will show you how predictable routing congestion from synthesis to tapeout eliminates unnecessary iterations, speeding up your overall turnaround time.
Janet Olson, Synopsys
Jun 09, 2009 | | | In-Design PV for Faster Time-to-Tapeout
Synopsys’ physical design and verification technologists will show you how in-design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.
Kerstin McKay, CAE Director, Physical Verification products, Synopsys
May 20, 2009 | | | Accelerating Time-to-SI Closure
View this webinar to learn how to use signoff-driven SI-closure to keep your schedule on track and your performance on target.
Dr. Henry Sheng, Synopsys; Dr. Jinan Lou, Synopsys
Mar 31, 2009 | | |
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