Design Challenges
Physical effects of semiconductors are becoming more and more interrelated. Each design decision can create unintended consequences. In addition to the old problems generated by wire capacitance, engineers can no longer manually balance the myriad effects such as leakage current, inductive noise or IR drop. Manufacturing processes and environmental variation can render your functional chip useless or economically unviable. Market forces are creating demands of higher volumes at lower and lower price points. Investors are losing their appetite for risk and paying a premium for predictable success. Designers must walk a tightrope of price and performance to reach their time-to-market goals.
- Exponential advances of Moore’s Law have facilitated creative solutions to the very problems they have created. Advances in computing power coupled to innovative algorithms enable the Galaxy Design Platform to perform two essential functions:
- Accurately model physical effects to guarantee timing
- Concurrently evaluate trade-offs between design goals
Accurate modeling of physical effects such as noise and power enable the advanced algorithms of the Galaxy platform to push the envelope of achievable performance and minimize the drain of pessimistic margins. This extra performance is like money in the bank. The concurrent optimization engines spend this savings to minimize power consumption, reduce area, lower test costs or increase yield. All of this increases productivity by saving time and iterations spent on fixing unintended consequences.
The Galaxy Platform lets designers do what they do best – design!