Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities

Unified Cell-Based and Custom Implementation Solution Key to Accelerating Time-to-Market

Synopsys Galaxy Custom Designer Enables First-pass Silicon Success on Foveon's Advanced Digital Sensor Product

Synopsys announced that Samsung Electronics' Foundry business (Samsung Foundry) has successfully taped out its first 32-nanometer (nm) system-on-chip (SoC) design using Synopsys' Galaxy™ Implementation Platform.

TSMC and Synopsys Collaborate to Validate Galaxy Custom Designer Solution with TSMC 28nm iPDK

Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, and X-FAB Silicon Foundries, the leading analog/mixed-signal foundry, today announced that X-FAB has expanded its support to include Synopsys’ Galaxy Custom Designer™ implementation solution.

Demanding AMS Project Design and Tapeout Schedule Met in 22 Days

Synopsys, Inc. today announced that Ubixum has used Synopsys' Galaxy Custom Designer™ implementation solution to successfully design its latest advanced image sensor chip.

Speeds RTL-to-GDSII Turnaround Time Through Look-ahead Constraint Analysis

Synopsys, Inc., today introduced its In-Design Rail Analysis™ capability to accelerate design closure. Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that TSMC selected Synopsys' Galaxy™ Implementation Platform for their new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler® synthesis and IC Compiler physical implementation solutions, and the PrimeTime® sign-off and Star-RCXT™ extraction solutions - the industry yardsticks for IC design sign-off. The new flow is now available for 65-nanometer (nm) designs with planned extensions into other process technology nodes.

HSPICE 2009.03 Delivers 2x Speed-up and Improved Silicon Correlation

Synopsys, Inc., today announced that Synopsys’ PrimeTime® PX solution, a key component of the Galaxy™ Implementation Platform and part of Synopsys’ Eclypse™ low power solution, has been successfully deployed at more than 175 semiconductor companies worldwide to perform highly accurate dynamic and leakage power analysis. Seamless integration within PrimeTime, the golden industry standard for timing and signal integrity signoff, has resulted in the selection of PrimeTime PX as the preferred power analysis solution at companies from all facets of the semiconductor industry.

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multi-media solutions, has adopted Synopsys’ PrimeTime® SI solution for static timing analysis (STA) and signal integrity (SI) signoff. MediaTek selected the Synopsys PrimeTime SI solution to streamline the signoff flow for its new cutting-edge system-on-chip (SoC) designs targeted at 65-nanometer (nm) and below process technologies.

Synopsys, Inc. today announced that Renesas Technology Corp. has deployed Synopsys' PrimeTime® advanced on-chip variation (OCV) capability to help accelerate timing closure for 65-nanometer (nm) and below system-on-chip (SoC) designs. PrimeTime advanced OCV analysis is an efficient, easy-to-adopt solution that employs adaptive derating to accurately account for random and systematic process variations across an integrated circuit (IC).

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Ubixum has adopted Synopsys' Galaxy Custom Designer™ solution, the industry's first modern-era mixed-signal implementation solution.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its Galaxy Custom Designer solution, the industry's first modern-era mixed-signal implementation solution.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that MediaTek, Inc., a leading semiconductor company for wireless communications and digital media solutions, has adopted Synopsys' IC Compiler for its next-generation, high-performance 65-nanometer (nm) system-on-chip (SoC) designs.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Oticon has taped out part of its next-generation digital signal processor (DSP) chipset for hearing-aid devices using Synopsys' IC Compiler design planning and place-and-route product, which is part of the Eclypse Low Power Solution.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its new Design Compiler® Graphical synthesis product that shortens implementation time for system-on-chip (SoC) devices by helping RTL designers avoid wire-routing congestion problems that typically occur during detailed route.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the qualification and immediate availability of Synopsys' IC Compiler for designs targeting TSMC's latest 45-nanometer (nm) process.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced its multi-core initiative to deploy advanced parallel, threaded and other optimized compute technologies across its Discovery™ Verification and Galaxy™ Design platforms, and Design for Manufacturing (DFM) solutions.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the availability of the industry's first concurrent hierarchical design system as part of the IC Compiler 2007.12 release. As designers migrate to smaller geometries, on-chip integration increases and design sizes mushroom, making hierarchical design almost mandatory.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that IC Compiler was used in a 45-nanometer (nm) system-on-chip (SoC) device of which Matsushita Electric Industrial Co., Ltd., the consumer electronics company behind the globally recognized Panasonic brand, has completed the tapeout, and which is entering volume production.