| Bridging Digital and Custom Domains |
Digital and custom (mostly meaning analog) design domains have remained stubbornly separate for a long time...But chips aren’t so neatly segregated now [and] the two flows don’t really work together well. Synopsys recently announced an improvement to this process that provides for a seamless, lossless transfer of information back and forth between domains.
Oct 17, 2011 |
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| Flexible Analysis is Key to Power Integrity |
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 17, 2008 |
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| Accellera Rolls Power Plan |
Welcome to EETimes, where engineers make their own connections. Meet your peers, discuss your work, find a mentor, talk tech, get advice, sound off, make some "inside" contacts, expand your career.
Oct 17, 2008 |
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| Synopsys bets on mixed-signal implementation market |
Synopsys, a provider in software and IP for semiconductor design and manufacturing, is betting on mixed-signal implementation market by unveiling its Galaxy Custom Designer(TM) solution, the industry's first modern-era mixed-signal implementation solution.
Sep 23, 2008 |
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| Full frontal attack |
War is invoked ad nauseum in the discussion of marketing. Partly because there are a lot of legitimate parallels. And partly because war reeks of testosterone and gives us a quick sharp adrenaline boost.
Sep 23, 2008 |
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| Synopsys revamps IC Complier with multi-threaded routing technology |
Developed from scratch by a team assembled specifically for their routing design experience, Mountain View, Calif.-based semiconductor design and manufacturing software supplier Synopsys Inc today rolled out Zroute, a new multi-threaded router that is completed integrated into the company’s IC Compiler physical design software.
May 27, 2008 |
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| Design Challenges Drive Need for New Routing Architecture |
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology. Increasingly manufacturability and yield have also become critical design objectives, especially for technology nodes at 90 nanometers (nm) and below.
May 27, 2008 |
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| Synopsys tries to organize its efforts in EDA multiprocessing |
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design. (OK, searching for extraterrestrials, maybe, but the economics are a bit different there.)
Mar 10, 2008 |
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| Complex SoC Testing with a Core-Based DFT Strategy |
With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically — making it almost impossible to test an entire design once it reaches manufacturing.
Feb 26, 2008 |
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| Test Methods Identify Small Delay Defects |
Today's systematic and more subtle random defects are not only decreasing yields, but are also increasing the number of test escapes, or defective parts per million (DPPM) shipped out.
Oct 30, 2006 |
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| Synopsys donates technology to Accellera low power effort |
SAN FRANCISCO — Top-tier EDA vendor Synopsys Inc. said Tuesday (Sept. 19) it has donated power management technology to the Unified Power Format (UPF) standardization effort of EDA standards organization Accellera.
Sep 19, 2006 |
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| Power integrity analysis for billion-transistor full-custom designs |
While the move to advanced process technologies has enabled levels of integration to reach new heights, engineers must now work harder than ever to realize those benefits.
Sep 17, 2006 |
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| Critical area optimizations improve IC yields |
The move to advanced nanometer nodes and new process materials is diminishing semiconductor designers’ ability to estimate and realize device yields.
Jan 09, 2006 |
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