Power-gating techniques are implemented in DSP designs to reduce leakage and standby power. Parts of DSPs can be powered down, while others, such as SRAM, cannot, as they are important for state retention. It is crucial to verify that the DSP functions correctly after the power-down cycle is completed. In addition, while some logic is powered down, the rest of the system must continue normal operation. The paper presents techniques that were used to verify the power-down methodology in Fcore4, a 4th generation DSP. The methodology can be reused for future wireless projects using new process technologies.
Prashanth Cherukuri, Mediatek Wireless, Inc

Power and Signal Reliability are becoming major area of concerns for Deep Sub Micron designs with reduced power supplies, reduced metal and via sizes and need for more integration. ARM uses Synopsys HSIMPlus to analyze Power and Signal Reliability issues seen in Memory Compilers.
Satinderjit Singh, ARM

Reducing power in an embedded processor targeted for high performance is becoming a necessity. Using off the shelf standard cell library and memory macros in 65nm, MIPS Technologies and Synopsys worked together to develop an automated design flow for reducing power in the MIPS32® 74K™ family of processor cores. 74K cores are the industry’s first fully synthesizable processors to exceed a GHz performance in a standard 65nm process. This paper describes several techniques employed for simultaneously meeting the performance target while reducing power.
Arvind Parihar Avishek Panigrahi, MIPS Technologies, Inc.

This paper will introduce a systematic approach of reducing power in complex clock-trees using IC Compiler’s low-power CTS (Clock Tree Synthesis) feature. Apart from discussing the various techniques in low-power CTS in ICC, this paper will also formulate a guideline of pre-analysis of a design during P&R (Place & Route) to identify the best method suited for clock-tree power reduction and how to achieve that using IC Compiler. Recommendation will also be provided on how to correlate the estimated clock-tree power in IC Compiler with sign-off (PT-PX). The goal of this paper is to guide the SoC designers to effectively use IC Compiler for clock-tree power reduction.
Hong Li, Narayanan Thondugulam, Santiago Fernandez-Gomez, Apple Shubharthi Datta, Synopsys, Inc.

Power gating is a valuable technique for reducing standby power in portable applications and comprises power rail switching of subsystems to cut leakage power. Power gating at the hardware level is now well supported in Synopsys design and verification tools, and the new UPF aware design flows are able to build on these. However from a system level design perspective inferring power gating, interface isolation and optionally state retention is not enough. This paper describes power management approaches for power gating with due attention to clocks, resets, testability and safe power sequencing - based on silicon proven results.
David Flynn, ARM

There are various strategies for leakage optimization and the optimization can be done at various stages of the flow: library development, synthesis, layout and timing closure. This paper describes a synthesis approach using hybrid-libraries and Vt-bucketing which gives much better leakage optimization than traditional synthesis strategies.
Sandip Patra, Broadcom Corporation

In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) noise, and it has a large impact on the conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting the power rail noise it is possible to drastically reduce the conducted emissions. Moreover, we propose an effective and practical methodology that can be seamlessly integrated into the standard design flows. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.
Patrice Joubert Doriol, Cristiano Forzan, Davide Villa, Davide Pandini, Renato Castellan, Daniele Cervini, Mario Rotigni, Giovanni Graziosi, STMicroelectronics Giuseppe Contarino and Egidio Marzorati, Synopsys

This work uses ESP-CV to simulate entire benchmarks using transistor level schematics and post-layout capacitance extraction. By using ESP-CV to translate a schematic netlist into a transistor level Verilog netlist, we can simulation thousands of benchmark cycles in minutes or hours compared with only tens of cycles using a fast spice simulator. This dif-ference in simulation speed allows us to simulate an entire benchmark instead of trying to guess what a good spice simulation window is. This flow has been used extensively for power estimation and optimization of custom macros integrated into Qualcomm's 45nm low power DSPs.
Stephen Bijansky, Bassam Mohd, Baker Mohammad, Qualcomm