With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial architectural design. The only way to do that is to model power consumption at the transaction level.
Aug 20, 2009

The widespread design of energy-efficient mobile devices, desire for green power, and government regulations on idle power have created a powerful market force for the pervasive employment of design techniques for reducing power. Voltage-control techniques have emerged as the most popular and effective means to reducing power.
Apr 10, 2009

This article discusses some of the architectural issues involved in implementing power-gating designs. In particular, it addresses the issues of partitioning, hierarchy and multiple power-gated domains.
Oct 15, 2008

A great deal of attention has been paid to low-power IC design, and for good reason – power consumption has become a critical, if not the most critical, issue in system-on-chip (SoC) design. While progress has been made, designers note that much more remains to be done to automate the low-power design and verification flow, especially at higher levels of abstraction.
Sep 01, 2008

Low-power designs have raised the bar on the verification effort. Designs optimized for power often employ complex design techniques that introduce their fair share of new bugs that are hard to track and fix.
Jul 28, 2008

Things have got so bad that companies supplying services to the chip designers now report a willingness, on their clients’ part, to ‘accept’ the risk of of a respin – the multi-million pound nightmare in which a project gets all the way to manufacture and fails.
Jul 22, 2008

The advent of handheld devices signaled an era of battery conservation. The demanding need of the consumer market to drive down the price of the handhelds called for the integration of several functions into a single gadget, and multiple applications running on a single gadget have put tremendous pressure on battery life.
May 20, 2008

Advances in process technology have enabled more transistors than ever to be packed in a die. The transistors have become smaller than ever. The net result is that the power density or power dissipated per unit area has gone up tremendously.
May 14, 2008

Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
Mar 04, 2008

This is the concluding part of a twoseries article, which commenced last issue. In this article, we’ll explore two DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests.
Feb 01, 2008

The very process of testing digital circuits routinely increases their dynamic power consumption to levels exceeding their power specification.
Jan 16, 2008

Accellera recently dilivered to the IEEE the Unified Power Format (UPF) as the new standard (IEEE P1801) for describing power intent in the industry's low power design flows.
Jan 14, 2008

Undertaking the design of a system-on-a-chip (SoC) is complex enough on its own merits. As is ever more the case, when power consumption is the primary design constraint, it becomes a task of enormous difficulty.
Jan 07, 2008

Deep-submicron systems-on-a-chip (SoCs) require a power-grid voltage drop of much less than 10% of VDD. Decoupling capacitors, or decaps, help achieve this goal by minimizing switching noise. Determining the amount of decap required for an SoC involves many considerations, but the task needn’t be a chore.
Oct 25, 2007

With more than one billion units shipped in 2006, cell phones have become the largest market segment for semiconductor content in the electronics industry.
Sep 01, 2007

The vision expressed in Moore's Law; that the number of transistors on a chip would double approximately every two years, has been driving the semiconductor industry for many process generations.
Aug 27, 2007

The demand for connectivity intellectual property (IP) for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as these standard interfaces are included in SoCs designed for applications such as single chip recordable DVD CODEC's and MP3 players.
May 07, 2007

The term "interoperability" is a lightening rod for both for customers and vendors in the EDA industry. While the concept is clear, enabling that interoperability proves to be more challenging since this moves beyond tool functionality alone.
Feb 02, 2007

Power reduction in advanced chip implementations requires a comprehensive approach that supports a broad range of design techniques.
Jan 15, 2007