Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs.
May 13, 2010

Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them.
May 13, 2010

Low Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation.
May 13, 2010

Low power designers have adopted increasingly aggressive techniques such as using multiple supply voltages. Multiple supply voltages imply a design with blocks and cells featuring multiple supply rails, further compounding the already daunting task of verifying low power designs. Incomplete or improper verification of such designs leaves open the possibility of functional failures in silicon.
Apr 06, 2010

Low-Power Engineering moderated a panel featuring industry experts discussing the topic of power management and verification. This article provides excerpts of their presentations, as well as the question-and-answer exchange that followed.
Mar 11, 2010

The Low-Power Design Portal has published serialized installments of Chapters 5 and 6 of the Verification Methodology Manual for Low Power (VMM-LP).
Feb 24, 2010

Low-power experts have consistently advised design teams to think about low power at the architectural level, and nothing has changed in that regard. What has changed are the numbers of possibilities for verification.
Jan 14, 2010

Low power design is not new. Extending battery life for mobile devices meant playing design tricks to conserve energy in every possible way. The desire to integrate a system on a chip and reduce overall cost led designers to rapidly adopt advanced manufacturing processes. The move to smaller manufacturing geometries accelerated the need for low power design because of the exponential increase in leakage power from smaller transistors packed in ever larger numbers on a single chip.
Jan 06, 2010

Verification of low-power designs, which until recently was a challenge for just a handful of all designs, is fast becoming every designer's problem.
Nov 25, 2009

Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together.
Sep 17, 2009

The EDA industry is in no way immune to the changes imposed by low power. If anything, power managed designs have had a far greater and more rapid impact than previous technological seismic shifts.
Sep 15, 2009

With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial architectural design. The only way to do that is to model power consumption at the transaction level.
Aug 20, 2009

EDACafé reviews the Verification Methodology Manual for Low Power (VMM-LP).
Jun 25, 2009

The latest generation of Synopsys’ Discovery verification platform upgrades the offering with new multicore simulation technologies, native design checks and low- power verification capabilities.
May 01, 2009

The widespread design of energy-efficient mobile devices, desire for green power, and government regulations on idle power have created a powerful market force for the pervasive employment of design techniques for reducing power. Voltage-control techniques have emerged as the most popular and effective means to reducing power.
Apr 10, 2009

This article discusses some of the architectural issues involved in implementing power-gating designs. In particular, it addresses the issues of partitioning, hierarchy and multiple power-gated domains.
Oct 15, 2008

Low-power designs have raised the bar on the verification effort. Designs optimized for power often employ complex design techniques that introduce their fair share of new bugs that are hard to track and fix.
Jul 28, 2008

Things have got so bad that companies supplying services to the chip designers now report a willingness, on their clients’ part, to ‘accept’ the risk of of a respin – the multi-million pound nightmare in which a project gets all the way to manufacture and fails.
Jul 22, 2008

The advent of handheld devices signaled an era of battery conservation. The demanding need of the consumer market to drive down the price of the handhelds called for the integration of several functions into a single gadget, and multiple applications running on a single gadget have put tremendous pressure on battery life.
May 20, 2008

Advances in process technology have enabled more transistors than ever to be packed in a die. The transistors have become smaller than ever. The net result is that the power density or power dissipated per unit area has gone up tremendously.
May 14, 2008

Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
Mar 04, 2008

This is the concluding part of a twoseries article, which commenced last issue. In this article, we’ll explore two DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests.
Feb 01, 2008

The very process of testing digital circuits routinely increases their dynamic power consumption to levels exceeding their power specification.
Jan 16, 2008

Accellera recently dilivered to the IEEE the Unified Power Format (UPF) as the new standard (IEEE P1801) for describing power intent in the industry's low power design flows.
Jan 14, 2008