Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distribution. More importantly, increases in SoC size and speed have brought heat dissipation and reliability issues such as electromigration and IR drop to center stage for a wide range of design applications.
Kajin Shi, Principal Consultant, Synopsys Professional Services Neel Desai, Product Marketing Manager, Synopsys Professional Services

The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments. These factors take on increased significance for teams that are new to constrained random verification techniques and advanced languages such as SystemVerilog.
Kwamina Ewusie, Senior Consulting Manager, Synopsys Professional Services Rajat Mohan, Product Marketing Manager, Synopsys Professional Services

Rapid changes in SoC power consumption have forced designers to rethink the methodologies they employ throughout the design flow to account for power-related effects. In addition to leakage power impacting battery life in mobile applications, increases in SoC size and speed have brought heat dissipation and reliability issues such as electro-migration and IR drop to center stage in virtually all chip designs at advanced process nodes.
Brandon Waldo, Senior Design Consultant, Synopsys Professional Services David Stringfellow, Staff Design Consultant, Synopsys Professional Services John Pedicone, Staff Design Consultant, Synopsys Professional Services

Today’s chip designers need to handle numerous and well-documented technical challenges associated with advanced process nodes, such as signal integrity and timing closure, leakage power management, functional verification, DFT integration and advanced physical design methodology for manufacturability and yield. However, survey data shows that design teams are also simultaneously dealing with significant and growing project-related challenges beyond the characteristics of the specific design itself, such as inconsistent design development across geographically distributed design teams, the ramping up of new sites, and correcting issues with 3rd party library and IP quality.
Michael Solka, Director of Physical Design Methodology, Synopsys Professional Services Ravi Srinivasan, Senior Product Marketing Manager, Synopsys Professional Services

When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP. (In this context, IP” is used in the broader sense, referring to both external and internal sources of design blocks to be integrated into an SoC.) The team must therefore use timing constraints from the providers of the IP, and these constraints vary greatly in their quality.
Michael Robinson, Senior Design Consultant, Synopsys Professional Services

In the increasingly competitive global electronics market, companies are focusing on the efficiency of their operations as well as the markets for their products. Systematic improvement of critical processes in the product development cycle is critical to achieve healthy levels of profitability. One of the most critical processes in the development of advanced electronics is the design and implementation of custom ASICs and ASSPs, which often become a gating item for product release. Improving the productivity of the chip design cycle can therefore pay big dividends in the product release schedule.
Michael Solka, Director of Physical Design Methodology, Synopsys Professional Services; Ravi Srinivasan, Senior Product Marketing Manager, Synopsys Professional Services

IR drop is a key factor affecting SoC performance, but few documented strategies for the fundamental and important task of setting the ideal IR drop target as early as possible in the chip’s physical design cycle are readily available.
Michael Solka, Director of Physical Design Methodology, Synopsys Professional Services Jonathan Young, Director of Physical Design, Synopsys Professional Services

Power integrity has become a crucial part of the system-on-a-chip (SoC) design flow because power-related issues can affect chip timing and even lead to complete device failure. Specifically, excessive rail voltage drop (“IR-drop”) and ground bounce can create timing problems and electromigration effects that impact a chip’s performance and reliability.
David Stringfellow, Staff Design Consultant, Synopsys Professional Services Kevin Knapp, Senior Design Consultant, Synopsys Professional Services

Designing deep submicron, multimillion gate ASICs for radiation sensitive environments requires a new approach to the traditional ASIC model. A collaboration between Honeywell and Synopsys combines advanced electronic design automation (EDA) tools and infrastructure with state-of-the-art silicon-on-insulator (SOI) manufacturing to address the requirements of next-generation military and aerospace chips.
Honeywell and Synopsys Professional Services Whitepaper

Signal integrity ("SI") issues such as crosstalk delay and noise are significant challenges for system-on-chip (SoC) designs at 130 nm and below. SI effects must be addressed prior to the final stages of physical design, or unpredictable timing-closure iterations, tapeout delays, chip failures, poor manufacturing yield - or all of the above - are likely to result. Fortunately, several years of experience with SI at very deep submicron geometries have led to efficient methodologies throughout the design flow for preventing, detecting and fixing SI effects.
Richard Nouri, Senior Design Consultant, Synopsys Professional Services Todd Beck, Senior Design Consultant, Synopsys Professional Services Jennifer Pyon, Corporate Applications Engineer, Synopsys

The rise in System on Chip (SoC) size and speed, as well as the increase in leakage current in Very Deep Sub Micron (VDSM) process technologies, have led to power consumption challenges across a broad range of designs that have not been viewed as supply limited or "low power" designs. Power issues may limit functionality or performance and significantly affect manufacturability and yield. Design techniques aimed at improving performance may therefore fall short if power is not considered. Fortunately, techniques such as multi-voltage islands and dynamic scaling of both clock frequency and threshold voltage can conserve power while delivering high performance.
Jim Flynn, Senior IC Design Engineer, Synopsys Professional Services Brandon Waldo, Senior IC Design Engineer, Synopsys Professional Services

Hierarchical design flows offer many benefits that can result in improved productivity when designing complex digital chips. Depending on specific design goals, hierarchical design practices and techniques are especially important in managing design constraints and static timing analysis (STA), but the effects of hierarchical design must also be considered in tasks such as static crosstalk analysis, clock-tree synthesis and design for test. As chip complexity continues to grow, these techniques become increasingly important.
Vijay Gullapalli–Senior Design Consultant, Synopsys Professional Services Kaijian Shi–Principal Consultant, Synopsys Professional Services

The physical implementation of very deep sub-micron (VDSM) designs benefits from good, up-front planning strategies, both in terms of schedule as well as quality of results. While the optimal planning strategy often varies from one design to the next, there are guidelines that can prove valuable in this critical phase of the design process
Sachin Idgunji, Staff Engineer, Synopsys Professional Services Steve Lloyd, Staff Engineer, Synopsys Professional Services Rick Mitchell, Staff Engineer, Synopsys Professional Services

Software development is becoming the dominant cost factor in electronics design. The ability to parallelize the traditional sequential process of software development trailing hardware development is crucial to get products to market as early as possible.
DesignWare

Recent market research indicates that today, the development effort for software running on 90nm and below has already surpassed the effort for the hardware development. It is the software which dominates and has become the bottleneck. In addition, low power and multi-core design requirements further complicate the software development process.
DesignWare