Verification remains the single most significant challenge in getting advanced SoC devices to market, and its share of the development process only gets bigger as chips get larger and more complex. Traditional verification methods simply cannot scale with chip complexity.

Advanced Methodologies for Functional Verification
Fortunately, new tools, methods and IP have emerged that dramatically improve verification productivity, and Synopsys is at the forefront of these new technologies. Synopsys Professional Services helps customers adopt new verification methodologies in their flows and rapidly deploy them across their entire SoC project. Consultants leverage expertise with Synopsys Discovery™ Verification tools and apply best practices based on the proven methodology defined in the popular book Verification Methodology Manual (VMM) for SystemVerilog, co-authored by Synopsys and ARM. The VMM methodology specifies advanced techniques such as assertions, constrained-random stimulus generation, and coverage-driven verification that result in a more efficient verification environment and increase the likelihood of first silicon success. Synopsys' extensive DesignWare® Verification IP portfolio, available for the industry's most popular interface protocols, easily integrates into VMM-compliant testbenches to significantly reduce testbench development time. Synopsys consultants help you take full advantage of the complete and integrated Synopsys verification solution to dramatically improve verification productivity and schedule predictability.

The VMM methodology (and precursor Reference Verification Methodology or "RVM") leveraged by Synopsys consultants defines widely-used verification best practices that enable users to take advantage of the same proven language capabilities, tool capabilities, and methodologies used by verification experts. Creating a design environment with VMM-compliant building blocks takes less time and eases cross-site collaboration as well as reuse at the block, system and project levels.

Rapid Prototyping
Synopsys’ Confirma™ Rapid Prototyping Platform provides a tightly integrated, comprehensive, rapid prototyping flow that accelerates the functional verification of FPGAs and ASICs. When used with the Confirma platform, the HAPS™ and CHIPit® line of ASIC prototyping boards and systems are ideal for IP and SoC design and verification teams who want to take advantage of FPGA-based prototyping to find “corner-case” hardware bugs or to start software development and integration in advance of ASIC availability.

Verification Services Highlights
Incorporating new verification flows and methodologies into existing infrastructure while simultaneously meeting project milestones can be challenging for any design organization. Synopsys Professional Services can help you achieve both. Through a combination of project assistance and flow consulting, our consultants help you gracefully upgrade to the latest tools and methods while minimizing risks to current project deliverables.

Using comprehensive RTL verification tools such as VCS®, Synopsys consultants support popular design and verification language standards such as Verilog, VHDL, SystemVerilog and SystemC™, enabling faster integration of complex SoCs built using multiple languages. Synopsys consultants also help users of Vera®, Synopsys' industry-leading testbench automation tool, build advanced constrained-random, coverage-driven testbench methodologies that co-exist and/or evolve into VMM-based environments.

Synopsys Professional Services' Verification Consulting services include:

• Developing a robust verification plan
• Architecting layered, automated testbenches
• Constructing bus functional models with both drivers and monitors
• Developing and integrating verification IP
• Generating constrained random stimulus
• Automating functional coverage collection to fine tune random stimulus
• Measuring and analyzing functional coverage
• Deploying SystemVerilog assertions (SVA) or OpenVera assertions (OVA)
• Customized flow consulting to migrate to advanced verification methods (e.g., directed or pseudo-random testing to constrained-random testing)
• Assistance deploying an ASIC prototyping flow and mapping your ASIC-targeted RTL to Synopsys’ HAPS™ or CHIPit® hardware

To get more information on how we can customize our services for you,  please contact us (web form) or call your local sales representative.