DataSheets

Accelerating Tool and Methodology Adoption

Take Full Advantage Of The Latest Tool Features And Methodologies

Design Flow Deployment

Optimize Your Design Flow To Address The Latest Design Challenges

Design Implementation Collaboration

Leverage Tapeout-proven Flows And Project Experience To Get Your Chip Done

Low Power Optimization and Verification

Implement Low Power Techniques To Optimize Your Chip’s Power Consumption

Predictable Silicon Sign-Off

Early Optimization For Physical Effects Improves Netlist Handoff

FPGA-Based Prototyping

Enabling Early System and Software Development

SoC Design and Verification

Achieve Rapid Design Closure By Applying Best Design Practices From The Start

Honeywell and Synopsys Enable Next-Generation Rad-Hard ASICs

Through the combination of a specially-targeted silicon-on-insulator (SOI) manufacturing technology and optimized design flow, Honeywell and Synopsys provide the industry's most comprehensive development capability for radiation-hardened (rad-hard) and radiation-tolerant ASICs.