Power consumption has always been a critical design constraint in chips targeted for battery-powered and mobile applications. With the migration to process geometries of 90-nanometer (nm) and below, power becomes a first order design priority on par with timing and signal integrity, impacting not only battery life but also a chip’s thermal management (e.g., packaging, cooling), yield, and long-term reliability. And, increasingly, power issues must be addressed throughout the entire design process, not only during the physical implementation.

Synopsys Professional Services has a unique combination of power methodology expertise throughout the design flow and design experience in System-on-Chip (SoC) power optimization that will enable you to meet your power budget and ensure a predictable chip-level power signoff. Leveraging the Eclypse™ Low Power Solution, our consultants will not only help you achieve tape-out success for your current project, but also transfer knowledge and proven methodologies to address power issues in your future projects. Typical areas of power optimization consulting include:

Dynamic power optimization
While RTL clock gating is a mature practice for reducing dynamic power, increasing design complexity with multiple clock domains and the resulting clock-tree design can be very challenging to integrate in the physical design. Synopsys consultants are experienced in deploying methodologies to reduce full-chip dynamic power using module-level, multi-stage, and hierarchical clock gating, gate-level power optimization and integrating the gated clock-tree in the physical design to ensure DFT, formal and sign-off compliant design.

Leakage power optimization
At 90nm process technologies and below, up to half of the power dissipated by transistors can be due to leakage current. To minimize this static power consumption, Synopsys’ consultants apply a power-aware design flow that optimizes the use of multi-threshold (multi-Vth) voltage cells from RTL synthesis to post-route optimization and ensure timing closure is achieved within power budgets. Our consultants have authored leading publications on power network synthesis methodologies for reduced leakage; techniques include power gating (e.g. MTCMOS) and sleep transistor design, placement, and optimization.

Multi-voltage design and integration
Varying voltages and dividing the chip into separately controlled voltage islands can provide significant power and energy savings, but this requires critical methodology changes throughout the entire design cycle, from architecture evaluation to RTL partitioning to full-chip signoff. Synopsys Professional Services can optimize your design flow to take advantage of the multi-voltage capabilities of the Synopsys Galaxy Design platform and help implement your multi-voltage SoC. Our consultants are also experienced in optimizing and integrating ARM® Intelligent Energy Management (IEM)-enabled SoCs.

Power planning and analysis
Due to increased routing complexity and growing reliability concerns in today’s complex SoCs, design teams must accurately estimate chip power consumption and design the power grid accordingly. Otherwise, the power grid may have significant IR-drop issues that negatively impact device functionality and performance. Synopsys Professional Services employs advanced methods such as IR-drop driven power network synthesis to create an optimal, robust power grid to improve tape-out predictability.

Chip rail analysis and signoff
The impact of power on final chip reliability necessitates thorough rail analysis and power network verification. Synopsys consultants use a proven signoff flow that analyzes the impact of IR-drop on performance, signal integrity, and test. With increasing challenges surrounding leakage current and the application of multi-voltage and power gating (also referred to as course-grain MTCMOS) our consultants can help mitigate the impact of “in-rush” current on long term reliability, signal integrity, and performance.