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Low Power Designs Made Easy: Create, Visualize and Debug Your Power Intent
This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Sebastian Brugnoli, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Mar 07, 2012 | | | Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification
In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011 | | | Bringing Up and Optimizing Software Power Management Using Virtual Prototyping
This webinar introduces a solution to the challenges that software developers face when bringing up or optimizing system power management.
Achim Nohl, Solution Architect, Synopsys
Jun 30, 2011 | | | Reduce Power Consumption 30% with Advanced Synthesis Techniques
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys and Rishi Chawla, Sr. Application Engineering Manager, Synopsys
Apr 14, 2011 | | | From Advanced OCV to UPF: Superior Results with the Lynx Design System
In this webinar you will learn how the built-in features of the Lynx Design System can help you achieve predictable design closure with superior results for low power chips.
Aditya Ramachandran, Lynx Design System, CAE, Synopsys; Neel Desai, Lynx Design System, Product Marketing Manager, Synopsys
Apr 12, 2011 | | | Successful Formality Equivalency Checking for Low-power Designs – Tips from the Experts
Learn from the expert how to successfully complete low power EC faster, and quickly address verification issues, with UPF in Formality.
Bob Hatt, Corporate Applications Engineer, Synopsys
Mar 15, 2011 | | | Accurate Power Analysis of Low Power Techniques Using PrimeTime PX
This technical webinar will explain how PrimeTime PX can be used to analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating. Attendees will learn how to further optimize their designs for power by analyzing which low-power techniques work best under differing conditions. You will also learn how to use PrimeTime PX to understand which modes of operation consume the most power.
David Le, Senior Manager, CAE, Implementation Group, Synopsys; Maria Tovey, Staff Engineer, CAE, Implementation Group, Synopsys
Aug 03, 2010 | | | Best of SNUG: Generating Low-Power ATPG Patterns using a Shift Power Effort
This technical paper presents experimental work and associated conclusions based on the simulation and silicon results on two different designs using Synopsys‘ new ATPG low-power algorithm.
Pascal Blanc, ST-Ericsson, France
Jun 10, 2010 | | | Best of SNUG: Energy-Efficient Processor Implementation with Eclypse Low Power Solution
This tutorial provides a technical case study of a 32nm Eclypse-based implementation of an ARM Cortex-A5 multi-processor with IEEE-1801 UPF-based power intent.
Alan Gibbons, Synopsys
May 06, 2010 | | | Static Verification Throughout the Low Power Design Flow
Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010 | | | Best of SNUG: Power-Aware Test Solution
This tutorial provides an overview of Synopsys’ power-aware and pin-limited testing features. It outlines how designers can generate patterns that are aligned with the functional power budget and reduce both dynamic and leakage power during scan testing.
Nikolaus Mittermaier, Synopsys, Germany
Apr 28, 2010 | | | Low Power Algorithm Exploration
Learn how to use the Synphony high-level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink.
Chris Eddington, Director of Product Marketing, Synopsys; Josefina Hobbs, Technical Solutions Architect, Synopsys
Jan 19, 2010 | | | Efficient & Accurate Memory Timing & Power Analysis using CustomSim
With the growing complexity of device models and the increasing impact on timing and power measurements from physical layout effects, accurate memory verification within a reasonable timeframe is a necessity. This webinar highlihgts memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time. Learn how Synopsys’ CustomSim™ solution is being used today for accurate and efficient memory timing and power analysis.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 16, 2009 | | | Fundamentals of Low Power IC Design
The power consumed by electronic devices has been on a downward path for many years as a result of the hard work and creativity of talented engineers. This course looks at the fundamentals of achieving the low power operation needed with nearly all of today's leading-edge chip designs.
Synopsys
Oct 01, 2009 | | | Everything You Always Wanted to Know About Low Power Verification
An understanding of the impact on verification from the deployment of low power design techniques is key to successful verification. Learn why verification has changed for low power designs and how Synopsys' VCS with MVSIM and MVRC comprehensively and accurately meet these challenges.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Prapanna Tiwari, Corporate Applications Engineering Manager, Synopsys
Aug 11, 2009 | | | A Structured Methodology for Verifying Low Power Designs
In this webinar, we focus on the bug types that are new to low power design and introduce a structured and reusable methodology highlighting VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Srikanth Jadcherla, Group Director of R&D, Synopsys; Janick Bergeron, Synopsys Fellow, Synopsys
Aug 11, 2009 | | | Increase Design Confidence with CustomSim
Learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.
Synopsys
Apr 28, 2009 | | | Verifying Complex Power-managed Designs
An overview of approaches that address the difficult task of verifying low power designs.
Synopsys
Dec 18, 2008 | | | Leakage Mitigation in ARM Processor-based Systems
Leakage mitigation techniques such as power gating, state retention and dynamic threshold scaling have been shown to significantly reduce standby power consumption.
Alan Gibbons, Principal Engineer, Synopsys; John Biggs, Consultant Engineer, ARM
Dec 18, 2007 | | |
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