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Featured White Papers |  Sweet Sounding SoCs: Why Analog Audio IP Lowers Costs and Sounds Better than Digital PWM | When determining the trade-offs between application requirements versus area and power, selecting the right audio drivers has become a critical decision for SoC designers. Audio drivers must efficiently address a wide variety of loading conditions such as line loads, earphone and headset loads, passive loudspeaker loads and more. For many years, solutions consisting of a digital-to-analog converter and continuous time drivers have co-existed with digital-centric Pulse Width Modulation (PWM)-based solutions to address the breadth of different audio loads. Perhaps the most important reason associated with choosing a digital-centric PWM-based solution is the perception that being purely digital its silicon area cost is lower than the analog implementations. However, this whitepaper shows that digital-centric PWM-based solutions do at most offset cost from silicon area to external components while failing to address a multitude of equally important application requirements besides low cost.
João Risques, Product Marketing Manager |
| | Understanding Clock Jitter Effects on Data Converter Performance and How to Minimize Them at the System Level? | This white paper shows that the characteristics of the sampling clock may determine the system performance, and that their effect is independent of the data converter that is being used in the system rather being a function of the characteristics of the signal being processed by the system (for example, its frequency). It also identifies the main sources of this clock uncertainty (clock jitter effects), providing guidelines and rules for system engineers to understand and minimize such effects, thus assuring system performance requirements.
Manuel Mota, Technical Marketing Manager |
| | Ethernet Quality-of-Service: New IEEE Specifications Driving a New Generation of Network Products | As designers look to their next-generation network designs, they are faced with a set of new challenges when developing products that incorporate the common Ethernet interface. To maintain Ethernet as a dominate and long-lasting network interface, the latest IEEE updates, which are targeted at improving networking systems' Quality-of-Service, will be critical to meet the demands of the consumer.
Lokesh Kabra, Senior R&D, Manager; John A. Swanson, Senior Staff, Marketing Manager |
| | Debugging SuperSpeed USB Software Using Virtual Prototypes | Software is a critical component for the development of USB-based designs. In efforts to start software development early and to make it as productive as possible, design teams are often utilizing virtual and FPGA prototypes for software development prior to silicon. This white paper describes how virtual prototype use models for hardware/software verification and the integration of the LeCroy analyzer software into Synopsys' DesignWare SuperSpeed USB verification environments help solve SuperSpeed USB IP development challenges.
Frank Schirrmeister, Director, Product Marketing; Tri Nguyen, R&D Engineer |
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Browse white papers by topic
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| | High Definition Video AFE: Far Beyond the ADC | | | Based on the importance of the video AFE as an essential part of nearly any consumer video product or personal computing display and on the need that these products deliver the highest-quality images, this paper explains that, although it is possible to implement a video AFE from a stand-alone ADC and a collection of separate analog components, the complex interactions between them make developing an optimized system a difficult task which can add significant delay and risk to a design cycle. These risks can be reduced using an optimized video AFE core from a third party IP provider ensuring your design delivers the best possible video quality and power efficiency in all of the operating modes.
João Risques, Product Marketing Manager |
| | | Reverse Process Migration from 65nm to 130nm in Under Three Months | | | Normally, a design team will tackle a new project on a new, smaller-geometry process and realize the benefits of increased performance and lower cost per chip. This white paper addresses the reverse of this situation, in which a functioning 65nm analog and mixed-signal design is “blown up” to a 130nm process to help mitigate the higher mask costs of the smaller geometry.
Bob Lefferts, R&D Group Director, Analog and Mixed-signal IP, Synopsys; Neel Gopalan, AMS CAE, Synopsys |
| | | Hi-Fi Audio: Unveiling the Hidden dBs | | | While looking at Hi-Fi Audio, high “dynamic range” is the most popular measurement used to assess whether an audio system is "clean" (providing high-quality audio experience), but should not be the only area of focus. This paper discusses dynamic range, the specification and hidden dBs that should be considered for the best audio experience possible.
Joao Risques, Product Marketing Manager |
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| | Improving I/O Virtualization Performance with PCI Express | | | This paper provides an introduction to the general concepts of virtualization and I/O virtualization (IOV). It also discusses how IOV is addressed within the PCI Express sepcification and how to support IOV with an existing PCIe interface. Additional topics include: Single-Root IOV, Function Level Reset, Alternative Routing ID and Address Translation Services.
Scott Knowlton, Sr. Product Marketing Manager |
| | | SuperSpeed Your SoCs with USB 3.0 IP | | | This whitepaper provides a comparison between the USB 3.0 and USB 2.0 standards, highlighting the new capabilities and advancements that have been made with this next-generation SuperSpeed USB standard including: performance, cables and connectors, power efficiency, USB model differences, hardware and software functionality, new protocol layers and streaming.
Dr. Robert Lefferts, R&D Director; Subramaniam Aravindhan, R&D Manager
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| | | Show Me the Next-Generation HDMI | | | Explore the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. In addition, this paper provides a tutorial on the new capabilities of HDMI 1.4 and its role in providing a richer, more straightforward user experience. Example case studies are also presented to illustrate how the HDMI Ethernet and Audio Return Channel (HEAC) feature simplifies cabling requirements.
Manmeet Walia, Product Marketing Manager |
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| | Accelerating Functional Closure: Synopsys Verification Solutions | | | This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when and how to implement code and functional coverage, and use it to achieve functional closure.
Hemendra Talesara, Synopsys Professional Services;
Neill Mullinger, Synopsys
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| | | Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog | | | Design teams are turning to advanced and unified verification methodologies that leverage multiple technologies to handle the biggest verification challenges. Constrained random verification leverages compute resources and functional coverage technology to provide more testing with less test code development. This paper, the first in a 2-part series, shows how to start performing constrained random verification quickly and easily with Synopsys' DesignWare VIP and VMM for SystemVerilog.
Charles Li, Corporate Applications;
Ashesh Doshi, Product Marketing
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| | | Advanced Techniques for Building Robust Testbenches with DesignWare® Verification IP and Verification Methodology Manual (VMM) for SystemVerilog | | | This paper is the second in a series and discusses the benefit of using constrained random verification and briefly recaps the first paper "Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog". The primary focus of the discussion is on using advanced techniques with Synopsys' DesignWare® VIP and VMM for SystemVerilog to build a robust, constrained random testbench. The techniques that will be discussed are: Constraints, Factories, Callbacks, Coverage and Scenario Generation.
Charles Li, Corporate Applications;
Ashesh Doshi, Product Marketing
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| | Reduce Power, Area and Routing Congestion - Analysis of a High-Performance On-Chip-Bus Interconnect | | | This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare® Interconnect Fabric used to meet the stringent timing requirements.
Fred Roberts, Corporate Applications Engineer |
| | | Coding Guidelines for Datapath Synthesis (Aug. 2009) | | | This document summarizes coding guidelines addressing the synthesis of datapaths. Two classes of guidelines are distinguished: 1) Guidelines that help achieve functional correctness and the intended behavior of arithmetic expressions in RTL code; and, 2) Guidelines that help datapath synthesis to achieve the best possible quality of results (QoR).
Reto Zimmerman, Principal Engineer |
| | | IP Solutions for Synchronizing Signals that Cross Clock Domains | | | This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another. In all cases, the issues covered here involve clock domains that are asynchronous with respect to one another. Along with each issue, one or more DesignWare® solutions are outlined. The topics and solutions include: basic synchronization; temporal event synchronization; simple data transfer synchronization; data flow synchronization; reset sequencing; and, related clock system data synchronization.
Rick Kelly, R&D Manager |
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| | A Survival Guide for Selecting High-Quality IP | | | This paper will explore three important determinants of IP quality: (1) Functional Correctness – extensive configurability of digital IP for standards interfaces and how an IP vendor verifies across a very large number of configurations. (2) Interoperability –probably the single most important criteria for IP and mistakenly equated with compliance, which is required but not sufficient on its own. (3) Ease of Integration –IP that is difficult to integrate will lead to schedule risk and increased cost of the SoC design.
Ed Bard, Sr. Director, Product Marketing;
Ralph Morgan, Vice-President, Engineering
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| | | The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator | | | While the IP landscape will always look different when seen through the eyes of SoC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.
David Chiapinni, Asic Project Manager, Matrox;
Massimo Vanzi, CEO, Accent;
Navraj Nandra, Director Product Marketing, Mixed-Signal IP, Synopsys
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| | | Life Begins at 65 – Unless You Are Mixed-Signal? | | | The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or, is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? This paper will answer these questions and more.
Navraj S. Nandra, Director of Product Marketing, Synopsys;
Reimund Wittmann, NOKIA Research Center, Bochum, Germany;
Massimo Vanzi, Accent, Vimercate, Milan, Italy
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