Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful connectivity standards. In today’s highly connected world, USB connections are found in the computing, consumer, mobile, industrial and automotive segments. Products are far ranging — from PCs and portable audio/video players to cell phones and digital TVs. With the trend of increasing data storage requirements driven by applications, such as high-definition video, combined with the desire to move this data quickly between host, storage, and portable devices, it was only a matter of time before there was a need to make this well-known standard even faster. This heralds the third-generation of this ubiquitous standard — the arrival of SuperSpeed USB 3.0.
Dr. Robert Lefferts, R&D Director, Synopsys; Subramaniam Aravindhan, R&D Manager, Synopsys

With an install base of over 1.1 billion devices worldwide, HDMI has become the de facto multimedia interface for all digital home and mobile/portable multimedia devices. The recently introduced HDMI 1.4 specification further reinforces the HDMI message of performance, reliability and simplicity. Features like the HDMI Ethernet and Audio Return Channel (HEAC), introduced in version 1.4, further simplify digital home theater wiring while adding new and innovative features. In addition, the HDMI 1.4 specification supports advanced media capabilities such as enhanced color spaces for digital still cameras, 3D modes and ultra-high resolution display formats (up to 4x higher than 1080p) that will be key features in the nextgeneration of premium multimedia entertainment consumer electronic products.
Manmeet Walia, Product Marketing Manager, Synopsys, Inc.

This application note describes how to configure and connect the DesignWare® SATA AHCI IP core to the Synopsys PHY in a multi-port AHB-based configuration, and provides an analysis of the expected throughput on each port based on assumed system parameters. The expectation is that a user should be able to take this example and insert actual system parameters to come up with a performance estimate. We will look briefly at the architecture of the core to enable a better understanding of the subsequent sections describing the configuration and performance calculations of the core. Also, note that while this document only discusses the performance of an AHB-based configuration, the option to select an AXI-based configuration will be available in the near future. Due to the nature of the AXI-bus, which allows for overlapping transfers, we expect an increase in the performance of a multi-port configuration.
Bjorn Widerstrom, CAE, Synopsys, Inc.

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion.
Fred Roberts, CAE, Synopsys, Inc.

For both analog-to–digital converters (ADC) and digital-to-analog converters (DAC), system-level specifications have a strong influence on several aspects of the converter’s design, including conversion rate, resolution, power dissipation and silicon area. With a special emphasis on broadband wireless applications, this white paper reviews the design trade-offs ranging from the converter’s sampling rate to the choice of single- or multiple-chip system partitioning. Understanding these choices enables chip architects and designers to optimize their systems in accordance with their particular constraints and the characteristics of the data converters. Today’s analog intellectual property (IP) choices are extensive, and the available ADCs, DACs, filters and other components offer versatile solutions that suit a wide range of requirements. System architects must make good system-level choices to get the best results from the analog signal-conversion IP - a crucial factor in gaining a competitive edge in any market.
Manuel Mota, Product Marketing Manager, Synopsys, Inc.

As more functionality converges onto a single device, it naturally leads to an increasingly large number of IP blocks on a chip. Before you consider developing or buying IP, remember not all IP is created equally and securing high-quality IP is imperative to getting your end design to market on time and on budget. This paper will explore three important determinants of IP quality: (1) Functional Correctness – Extensive configurability of digital IP for standards interfaces and how an IP vendor verifies across a very large number of configurations is an excellent indicator of how the IP will function within your system. (2) Interoperability – This is probably the single most important criteria for IP. Often this is mistakenly equated with compliance, which is required but not sufficient on its own. (3) Ease of Integration – This is directly related to time-to-market. IP that is difficult to integrate will lead to schedule risk and increased cost of the SoC design.
Ed Bard, Sr. Director, Product Marketing, Synopsys, Inc.; Ralph Morgan, Vice-President, Engineering, Synopsys, Inc.

Audio processing is essential to electronic applications such as mobile phones, MP3 players, set-top boxes, and a host of other products where size and power consumption are critical design criteria. Additionally, high-end products, such as digital TV and smart phones, need to set themselves apart from competing products by adding value with high quality HiFi (High Fidelity) audio capabilities. While looking at Hi-Fi Audio, high “dynamic range” is the most popular measurement used to assess whether an audio system is “clean” (providing high-quality audio experience), so it is arguably the most important audio specification. But by only focusing on a given audio system’s dynamic range, two effects are ignored: (1) most mainstream audio system’s dynamic range reaches levels on par or even exceeding the 100 dB’s that the human ear can perceive, making it difficult to discern which system delivers the best quality; and (2) other equally important factors that determine the overall audio quality are overlooked, such as linearity, channel separation, phase linearity, and so on.
Joao Risques, Product Marketing Manager, Synopsys, Inc.

Emerging from a host of competing technologies, DDR2 and DDR3 SDRAM (“DDR”) have become the dominant off-chip memory storage solution for system-on-chip (SoC) designs. With high volumes driven by the PC market, stability of supply, and attractive pricing, DDR has defeated all of the contenders including QDR SRAM, RLDRAM, Rambus DRAM and other memory technologies to take the RAM crown for embedded applications. Unfortunately, many SoC designers are unfamiliar with the realities of the DRAM standards, typical DRAM applications and the DRAM market. This paper presents ten guiding principles for embedded DDR interfaces, many of which the DRAM standards and vendor data sheets do not explain
Graham Allan, Sr. Manager, Product Marketing, Synopsys Inc.

By using intellectual property (IP), system-on-chip (SoC) designers can now easily incorporate an HDMI interface in leading edge process technologies such as 90 nm, 65 nm, and 40 nm processes. This eliminates the need for a separate IC, delivering significant power and cost savings. Products for the digital home and portable consumer electronics constitute the main target applications for the HDMI interface.
Luis Laranjeira, Sr. R&D Manager, Synopsys, Inc.

This paper provides a brief discussion of DDR source-synchronous timing concepts and describes five different timing domains. It shows how designers can meet timing budgets for double data rate, single data rate, and cross-domain (clock to strobe) timing domains. Finally, it shows how to improve interconnect timing by reducing crosstalk, inter-symbol interference, reflections and skew, and by controlling simultaneously switching output (SSO) effects.
John Ellis Senior Staff R & D Engineer, Synopsys, Inc

Today's IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager Eric Huang, Product Marketing Manager October 2007

PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP). The objective of this white paper is to equip the reader with a broad understanding of PCI Express and the design challenges essential to successful PCIe implementation.
DesignWare

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys' complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target applications. It mentions the market growth trends and highlights typical application areas for 10G Ethernet.
DesignWare

The intent of this article is to provide an overview of the newly introduced features for the DesignWare Cores WiUSB Controller (DWC_uwb) core. In this article, customers would gain insights into the technical details of the new features as well as the benefits these new features bring to the applications. Furthermore, the technical advantages of the DWC_uwb core are explained to provide customers a better understanding of the core design.
DesignWare

A Gigabit Ethernet controller incorporating a PCI Express interface takes advantage of the high-throughput, low latency capabilities of PCI Express to deliver true gigabit performance. These enhanced capabilities allow for optimal sizing and utilization of on-chip memory, providing significant power and area savings. This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital IP core into a Gigabit Ethernet design. Techniques for configuration of the PCI Express IP are presented that achieve the lowest power, lowest latency and smallest memory size, as well as optimal system performance.
DesignWare

Consumers have embraced the convenience of each wireless revolution – from landlines to cell phones, wired networks to Wi-Fi networks. Our need for wireless connectivity, familiarity with the USB standard and the favorable economics of Certified Wireless USB, will ensure it is a success. Certified Wireless USB technology from the USB Implementers Forum (USB-IF) will be adopted more rapidly than Wi-Fi, and even outpace the take-up of wired Hi-Speed USB 2.0 devices. This paper provides an up-to-date report on the status of Certified Wireless USB technology. It explores the favorable economic factors and technology benefits that Synopsys believes will drive rapid adoption of this new standard.
Eric Huang, Product Marketing Manager, Synopsys, Inc.

Today's IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager Eric Huang, Product Marketing Manager October 2007

While the IP landscape will always look different when seen through the eyes of SoC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.
David Chiapinni, Asic Project Manager, Matrox Massimo Vanzi, CEO, Accent Navraj Nandra, Director Product Marketing, Mixed-Signal IP, Synopsys

The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or, is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table will analog designers of Bob Pease’s generation sit: the IP provider or the chip company? Or, are their skills redundant for the 65 nm analog challenges?
Navraj S. Nandra, Director of Product Marketing, Synopsys Reimund Wittmann, NOKIA Research Center, Bochum, Germany Massimo Vanzi, Accent, Vimercate, Milan, Italy

The physical layer is responsible for the transmission of the raw bit stream over the PHYsical transport medium and is the lowest layer within the OSI network model. With high-speed interfaces such as the serial protocols USB 2.0, PCI Express®, SATA, and DDR2, the PHY provides the bridge between the digital and modulated parts of the interface. The trend is to integrate these mixed-signal interfaces into SoC’s that are manufactured in digital logic deep sub-micron technologies with channel lengths of 65-nm and 45- nm.
Navraj S. Nandra, Director of Marketing Mixed-Signal IP, Synopsys Inc.

The demand for connectivity IP for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as standard interfaces in applications such as single chip recordable DVD CODEC’s and MP3 players. In order to stretch battery life of these chips, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes, enabling production of very low-power chips for these mobile platforms and small-form factor devices.
Navraj S. Nandra, Director of Product Marketing, Synopsys

DDR2 SDRAM is an increasingly common memory solution for designs requiring improved data bandwidth capabilities and enhanced signaling features. However, the benefits of DDR2 SDRAM are coupled with significant physical implementation challenges at data rates above 400 Mbps. This paper discusses how using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks, such as interoperability, associated with combining discrete memory subsystem blocks.
David Wallace, Product Marketing Manager, Synopsys, Inc.

The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (titled DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted to mobile and high volume consumer applications. This offers designers a choice of highly-differentiated USB PHY cores for 0.13-micron processes and below.
Gervais Fong, Product Marketing Manager, Synopsys, Inc

This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. It will discuss the power of constrained random simulation using an object-oriented testbench and verification IP to provide better control and reuse. It will then show how this leads to more effective use of available resources such as simulation compute farms and engineers’ time. Since coverage is a measure of how effectively the design is being verified, this paper will address when and how to implement code and functional coverage and use it to achieve functional closure.
Hemendra Talesara: Synopsys Professional Services, Neill Mullinger: Synopsys

Design teams are turning to advanced and unified verification methodologies that leverage multiple technologies to handle the biggest verification challenges. Constrained random verification leverages compute resources and functional coverage technology to provide more testing with less test code development. Setting up a constrained random test environment, however, can seem like a difficult task, especially when you consider that environments need to be flexible, scalable, and reusable. The infrastructure for constrained random verification requires more planning and structure, but the benefits in the end are well worth the investment. This paper shows how to start performing constrained random verification quickly and easily with DesignWare VIP and VMM for SystemVerilog.
Charles Li, Corporate Applications, Ashesh Doshi, Product Marketing

This paper is the second in a series. It discusses the benefit of using constrained random verification and briefly recaps the Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog paper. The primary focus of the discussion is on using advanced techniques with DesignWare VIP and VMM for SV to build a robust constrained random testbench. The techniques that will be discussed are: Constraints, Factories, Callbacks, Coverage, Scenario generation
Charles Li, Corporate Applications, Ashesh Doshi, Product Marketing

This paper shows how to perform advanced stimulus generation using DesignWare Verification IP and VMM for SystemVerilog. It focuses on two key topics - Exceptions and Scenario Generation. Exceptions represent protocol deviations or injected errors. Although errors are to be avoided in design, creating non-compliant conditions is an important part of the verification effort. In addition, it is fairly easy to generate a stream of discrete transactions each one unrelated to the others to verify the design but often protocol traffic really occurs as sequences. The ability to create scenarios which are sequences of protocol activity is the key to effectively testing and verifying the design. This paper goes into the details of successfully creating exceptions and generating scenarios.
Charles Li, Corporate Applications

This document summarizes coding guidelines addressing the synthesis of datapaths. Two classes of guidelines are distinguished: - Guidelines that help achieve functional correctness and the intended behavior of arithmetic expressions in RTL code; - Guidelines that help datapath synthesis to achieve the bestpossible QoR (quality of results)
Reto Zimmerman, Principal Engineer, Synopsys, Inc.

This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another. In all cases, the issues covered here involve clock domains that are asynchronous with respect to one another. Along with each issue, one or more DesignWare solutions is outlined. The topics and solutions include: Basic synchronization — DW_sync; Temporal event synchronization — DW_pulse_sync, DW_pulseack_sync; Simple data transfer synchronization — DW_data_sync, DW_data_sync_na, DW_data_sync_1c; Data flow synchronization — DW_fifo_s2_sf, DW_fifo_2c_df, DW_stream_sync; Reset sequencing — DW_reset_sync; Related clock system data synchronization — DW_data_qsync_hl, DW_data_qsync_lh.
By Rick Kelly, R&D Manager, Synopsys, Inc.

With a rich library of DesignWare Floating-Point IP, chip designers have many implementation choices that can significantly affect the final quality of results. These choices are especially important when using synthesizable IP (such as the IP in the Synopsys DesignWare® Library), where good implementation choices can optimize the tradeoffs between area/delay and accuracy. While the IP can provide extremely high levels of accuracy, pushing accuracy higher than the application requires simply compromises area and/or performance. This whitepaper describes several types of flexible tradeoffs available to designers, including the benefits of specifying complex floating-point operations rather than multiple separate operations.
Alex Tenca, Engineering Project Leader, Synopsys

To successfully develop an AMBA™ 3 AXI™ protocol-based design in the shortest time requires a comprehensive set of synthesizable IP, verification IP and an automated method to assemble the entire SoC subsystem. The AMBA 3 Advanced eXtensible Interface (AXI) protocol builds on the benefits of the AMBA 2.0 standard offering greater performance and flexibility. But with this flexibility comes complexity. This paper shows how the DesignWare® IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate high speed designs based on the AMBA 3 AXI protocol.
Mick Posner, Synopsys, Inc

The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher performance requirement, as the bottleneck is inherent in the existing bus infrastructure. This paper examines the advantages of the new AMBA® 3 Advanced eXtensible Interface (AXI™) protocol for on-chip bus infrastructure, and how it revolutionizes the future of high-performance system-on-chip (SoC) interconnect. It describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency and low-power designs. It also examines the verification tools and intellectual property (IP) necessary to successfully complete design and verification in today’s reduced development design cycle.
Mick Posner—Synopsys, Darrin Mossor—Synopsys

This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths: Guidelines that help achieve functional correctness and intended behavior of arithmetic expressions in RTL code. Guidelines that help datapath synthesis to achieve best possible QoR (Quality of Results).
Reto Zimmermann – Synopsys

To meet increasing time to market pressures, designers have been using more IP to reduce the amount of new code that needs to be created for the design. Additionally on-chip bus standards such as AMBA® have been widely adopted, providing designers with a standard that allows them to integrate multiple complex IP blocks as a subsystem into an SoC. This article describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable AMBA subsystem with IP architected and packaged for use and intelligent assembly and configuration. The focus of this article will be on the assembly of the subsystem with synthesis, verification and packaging of the subsystem summarized.
John Swanson, Product Marketing Manager, Solutions Group

Now more than ever, developers of complicated SoC design rely on silicon IP (SIP) both internally developed and from third parties to achieve their time-to-market goals. Too often, SIP providers have oversold the capabilities of their products. It’s time for a new supplier-buyer relationship. After nearly 10 years of practice, SIP vendors must deliver a “Total Quality Experience” to buyers. But judging the quality of SIP is more than just answering yes to rows of questions in a matrix. Quality is measured most effectively through direct customer feedback and systematic quality investigation. SIP providers must now step up and deliver a new experience for their SoC customers.
Kevin Walsh, Director of Marketing

The title might seem like marketing jargon. But often, if you create an interesting expression, the words help conjure up a picture of what is actually taking place. The frame of this picture is IP or SIP. IP providers will play a central role in the next big landscape change in the semiconductor supplier market, reversing a trend that began over forty years ago—the disaggregation of the supplier market in semiconductors. Reverse disaggregation will drive the creation of a new supply chain for the development of a new generation of products, full featured and assembled at zero cost. IP will influence how the new supply chain is created, reversing the disaggregation that has marked the industry until now.
Kevin Walsh, Director of Product Marketing, Synopsys, Inc.