By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars

This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Gervais Fong Product Marketing Manager, USB PHY IP

Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer

DisplayLink demonstrates how it uses DesignWare SuperSpeed USB 3.0 and HDMI IP to show full HD resolution over USB 3.0 by taking video directly out of USB 3.0 on the PC, convert it to HDMI and display it directly to a high-resolution monitor.
Gervais Fong, Product Marketing Manager, USB PHY IP Dennis Crespo, Vice President of Marketing, DisplayLink

Synopsys shows how fixed video and audio patterns are transmitted by the DesignWare HDMI TX controller and PHY. See the image quality improve as resolution of video test pattern is increased from 480p to 720p to 1080p, 60 Hz frame formats. Also see the EDID info collected by TX Controller/PHY Display Data Channel (DDC) from the sink device (DTV) to support negotiation and find the best supported color format and frame rate.
Manmeet Walia, Product Manager for Mixed-Signal PHY IP, Synopsys

See Synopsys and MCCI demonstrate how music can be synchronized in a matter of seconds in a USB 3.0 media player compared to minutes in a USB 2.0 media player. The demonstration consists of the Synopsys DesignWare® SuperSpeed USB Digital Controller and MCCI SuperSpeed USB Software on an FPGA hardware platform.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI

TI demonstrates SuperSpeed USB interoperability and USB 2.0 backward compatibility. The demo showcases TI's TUSB80x0 Hub and TUSB9260 SATA bridge controller with the Synopsys DesignWare SuperSpeed USB 3.0 IP
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI

See high-definition video using the DesignWare® SuperSpeed USB 3.0 xHCI Host and Device Controller implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video streaming from a standard PC running on a Linux operating system with a SuperSpeed USB 3.0 xHCI Host Stack, into mass storage device.
Eric Huang, Product Marketing Manager, USB Digital

See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s. The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
Scott Knowlton, Sr. Produt Marketing Manager, Synopsys

SuperSpeed USB 3.0 delivers 10x the data transfer rate of USB 2.0, targeting next-generation camcorders, portable media players, and Smartphones. USB 3.0 operates at a fraction of the power-per-bit of USB 2.0, while transferring data at 5 Gbps with up to 3 meters of cable. This tutorial examines the signal integrity issues and challenges when adding USB 3.0 into SoCs, as well as how equalizers, 8B10B coding, clock-data-recovery, and channel loss impacts USB 3.0 serial-links.
Bob Lefferts, Director of R&D

See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device digital controllers in a single demonstration. In this video, Synopsys shows interoperability between the DesignWare SuperSpeed USB 3.0 controllers and a USB 3.0 mass storage device, USB 2.0 flash controller and USB 1.1 mouse.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP

See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions.
Mat Loikkanen Sr. R&D Engineer, Synopsys; Mick Posner Sr. Product Marketing Manager, Synopsys

Serial ATA (SATA) is the mass storage interface of choice for hard disk drives, optical disk drives and the newer NAND flash-based solid state drives, making the architecture and feature set of the SATA interface one of the most important aspects of the SoC design. This tutorial will describe a set of easy-to-implement methods and best practices to help achieve performance goals, while maintaining low power consumption for the overall system.
Bjorn Widerstrom

Join us in the Synopsys lab to see proven interoperability between the Texas Instrument’s USB 3.0 transceiver and the Synopsys DesignWare USB 3.0 host and device controller implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI

See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang, Director of Marketing, Global Unichip Corp.

Join Synopsys in our lab to see actual USB 3.0 data transfer utilizing the DesignWare Superspeed USB Host and Device Controllers implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video, streaming from the device into the host with a measured throughput of 460 MB/s utilizing the Lecroy CATC analyzer.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP

See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.
Graham Allan, Product Marketing Manager, DDR IP

Join Synopsys in our lab to see how we deliver a compliant, robust PCI Express 2.0 PHY and enable visibility into the link performance through unique on-chip diagnostics.
Navraj Nandra, Marketing Director MSIP

The video will take you through our silicon verification board set up, show the unique tunability feature and highlight the extensive characterization process of the USB 2.0 nanoPHY.
Gervais Fong, Product Marketing Manager, USB PHY IP