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USB IP Blog: To USB or Not to USB
Covering the latest trends and topics in USB IP.
Eric Huang
The Eyes Have it: A Mixed-Signal IP Blog
This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.
Navraj Nandra
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K-Micro Meets High-Performance Requirements for Home Networking SoCs with DesignWare Data Converter IP
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Synopsys Showcases Silicon-Proven DesignWare IP Solutions for SuperSpeed USB....
Synopsys Offers Designers Many Opportunities for Design Success at EDSFair
Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions
Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for....
Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed....
Synopsys Expands DesignWare Data Converter IP Portfolio with 40-nm Solutions
Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm....
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One-stop shop provides easy-to-use USB 3.0 IP
Nikkei Electronics Asia: 1.066Gbps Signal Throughput in DDR3 with 4-Layer Boards
Chip Design: Adopting New Design Techniques in Analog IP to Optimize Power and Performance in Consumer Electronics
Chip Design: When It Comes To Intellectual Property, Size Matters
EDA DesignLine: The best of both worlds: Optimizing OCP slave memory behavior
Chip Design: Verifying USB 3.0 designs - it’s all about the integration
EDN: IP Quality Lies Beyond Compliance Testing
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Blogs
USB IP Blog: To USB or Not to USB
The Eyes Have it: A Mixed-Signal IP Blog
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Success Stories
K-Micro Meets High-Performance Requirements for Home Networking SoCs with DesignWare Data Converter IP
Netronome Selects Synopsys’ DesignWare DDR Controller and PHY IP for High-Performance Network Processor SoC
Ambarella Delivers Innovative Hybrid Camera SoC Platform with High-Quality DesignWare USB and Ethernet IP
GUC Delivers Low Power, High-Performance Solid State Drive SoC Platform with DesignWare SATA IP
Synopsys’ DesignWare® IP Helps STMicroelectronics Speed Time-to-Market for STM32 Connectivity Line of SoCs
Complete DesignWare IP Solutions Enable ViXS to Achieve First Pass Silicon Success for Advanced Video Processing SoC
ChipWrights Achieves First-Pass Silicon Success and Meets Aggressive Schedule with High-Quality DesignWare USB and Ethernet IP
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White Papers
SuperSpeed Your SoCs with USB 3.0 IP
Show Me the Next-Generation HDMI
DesignWare SATA AHCI Host Controller - Understanding Multi-Port Configuration and Performance
Reduce Power, Area and Routing Congestion - Analysis of a High-Performance On-Chip-Bus Interconnect
How System-Level Trade-offs Drive Data Converter Decisions
A Survival Guide for Selecting High-Quality IP
Hi-Fi Audio: Unveiling the Hidden dBs
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Webinars
Managing System Bandwidth With a High-Performance On-Chip Bus
Understanding HDMI: The Evolution, Ecosystem and Latest 1.4 Specification
Reduce Energy Consumption for Datapath Designs
SuperSpeed your SoC with USB 3.0
Virtualization of PCI Express I/O Devices
Buying Time: Using Signal Integrity and Common Sense to Meet Timing Margins for High Speed Memory Interfaces
Guidelines for Mixed-Signal PHY IP Integration, Debug and Test
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Videos
Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability
DesignWare DDR3/2 IP Demo at 1600 Mbps
DisplayLink Streams Uncompressed HD 1080p Video Using Synopsys’ USB 3.0 IP
Silicon-proven DesignWare® HDMI TX Controller and PHY IP on Synopsys’ HAPS-51 Platform
Synopsys and MCCI SuperSpeed Media Player Demonstration
TI Demonstrates USB 3.0 Interoperability at IDF with DesignWare IP
DesignWare IP for PCI Express 2.0 Complete Solution Demo
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DesignWare Technical Bulletin - Q3-08
DesignWare Technical Bulletin - Q2-08
DesignWare Technical Bulletin - Q1-08
DesignWare Technical Bulletin - Q4-07
DesignWare Technical Bulletin - Q3-07
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