| Programmable Hardware Accelerators Made Easy: Implementing Custom Processors without Compromising Performance, Power or Area |
Learn how custom processors or ASIP can provide the right trade-off between flexibility and power, performance and area requirements.
Drew Taussig, Corporate Applications Engineer, Synopsys
Feb 28, 2012 |
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| Managing Hierarchical, Low Power Design Challenges with the Lynx Design System |
In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.
Chad Gamble, Synopsys
Jan 17, 2012 |
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| Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping |
See examples of how FPGA-based prototyping can be used to deal with the high data rates of multi-channel, wideband digital systems while reducing systems validation and hw/sw integration costs.
Neil Songcuan, Product Marketing Manager, Synopsys;
Gary Goncher, Applications Engineer and System Architect, Tektronix
Jan 11, 2012 |
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| Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications |
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications
Ting-Jia Hu, Sr. Program Manager for DesignWare NVM IP, Synopsys
Jan 10, 2012 |
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| Get the Most from Your HSPICE Simulation |
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011 |
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| LTE-A Physical Layer Design: Downlink |
Learn about the LTE-A standard (Rel.10) with a focus on the downlink configuration, and understand the main enhancements over LTE Rel.8 and their implication on the overall system complexity.
Vafa Ghazi-Moghadam, R&D Engineer, Synopsys
Nov 15, 2011 |
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| Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design |
Learn how high-level synthesis can be used to efficiently create multi-rate hardware for ASIC and FPGA while keeping algorithm development simple.
Chris Eddington, Product Marketing, High-Level Synthesis, Synopsys
Nov 03, 2011 |
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| Expediting Design Schedules with DC Explorer - Qualcomm’s Experience |
Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation.
Matt Baker, Staff Engineer, Qualcomm; Sandra Ma, Sr. Director, Corporate Application Engineer, Synopsys; Liz Chambers, Product Marketing Manager, Synopsys
Nov 01, 2011 |
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| Meet Your Schedule with New ECO Verification and Other Enhancements in Formality |
Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.
Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011 |
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| Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks |
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011 |
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| Faster Clock Analysis and Debug |
Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Karen Linser, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Oct 25, 2011 |
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| Introducing the DesignWare ARC 32-bit Processor Family for Embedded Applications |
Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area; performance exceeding 1.5 DMPS/MHz; and power-efficiency of less than 2uW/DMIPS at 28-nm.
Steve Tateosian, Product Marketing Manager ARC Processors, Synopsys
Oct 25, 2011 |
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| Addressing Challenges at 20nm: A Foundry and EDA perspective |
Synopsys and Samsung jointly present some of the key challenges of designing and manufacturing at 20nm. Learn about solutions that address these challenges.
KK Lin, Director, Foundry Design Enablement, Samsung; Tong Gao, R&D Fellow, Synopsys
Oct 24, 2011 |
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| Extraction Features & PDKs for Accurate Analog Design |
Learn how StarRC new custom design features including 3D symmetric net extraction, optimized PCELL solution, and qualified PDK support, enable accurate and productive analog/mixed-signal design.
Krishnakumar Sundaresan, Principal Engineer/Manager, CAE, Synopsys
Oct 20, 2011 |
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| Addressing the Challenges of Designing an AMBA(R)-based SoC with a PCI Express(R) Interface |
The Webinar will explore trade-offs and implementation issues through lessons learned from the development of Synopsys DesignWare IP for PCI Express solutions and the customers that have used them.
Frank Kavanagh, Senior Engineering Manager, DesignWare Digital Controllers for PCI Express, Synopsys
Oct 20, 2011 |
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| Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle |
Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011 |
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| Chinese Version: Build Low-power, high-performance mobile SoCs with complete MIPI solutions |
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Haopeng Liu, FAE, Synopsys
Oct 17, 2011 |
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| Using High-Level Synthesis and Open Source Imaging Libraries to Streamline ASIC/FPGA IP Development |
Introduces a HLS flow from OpenCV (Open Computer Vision) environment using Synphony C Compiler. It will cover techniques in using C++ classes and templates to make re-usable imaging libraries.
Chris Eddington, Product Marketing Manager, Synopsys, Inc.
Oct 13, 2011 |
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| Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification |
In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011 |
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| New Features in TCAD Sentaurus: September 2011 Release |
The latest release delivers new capabilities in advanced structure generation, new models in process and device simulation and new methods for modeling semiconductor device variability.
Karim El Sayed, Director, TCAD R&D, Synopsys; Sudarshan Krishnamoorthy, TCAD Technical Marketing Manager, Synopsys
Oct 06, 2011 |
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| Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications |
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.
Martin Niset, Senior Product and Test Engineering Manager, Synopsys
Oct 05, 2011 |
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| Advanced Fault-Injection Methods for Automotive Safety Critical Systems |
Learn about fault-tolerance mechanism and fault-injection techniques and HW fault-tolerance mechanisms available in "state-of-the-art" Micro-Controller Units.
Victor Reyes, Technical Marketing Manager, Synopsys; Manfred Thanner, Technical Staff Systems Engineer, Freescale Semiconductor
Sep 29, 2011 |
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| VCS Productivity Technologies - Reducing the Growing Verification Cycle |
Learn about VCS’ most recent technology advancements and new features enabling productivity in the following key areas: performance and capacity, verification planning, coverage and debug.
Michael Sanie, Director of Product Marketing, Synopsys; Shekhar Mahatme, Senior Staff Application Engineer (Verification Methodology), Synopsys
Sep 21, 2011 |
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| Divide and Conquer: Faster FPGA Delivery using Hierarchical, Parallel Design Development |
Lean how to use "divide and conquer" hierarchical approaches for parallel machine execution or team-based design, and how to develop, tweak and debug your FPGA design efficiently.
ngela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Sep 20, 2011 |
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