This quarterly newsletter provides you with the latest information on DesignWare IP including in-depth technical articles, whitepapers, videos, upcoming webinars, product announcements and more. As the industry's trusted IP provider, Synopsys is committed to providing you with the resources you need to help you lower integration risk and speed time-to-market.
Featured Articles
- SuperSpeed USB 3.0 Rises in Smartphones - It is expected that by 2014, smartphone manufacturers will transition from USB 2.0 to USB 3.0 to save power, improve performance and add more functionality. This article discusses how you can be ready for the next-generation of SuperSpeed USB-capable smartphones.
Read more - Embedded Design Prototyping Relies on IP Model Availability - As demand for SystemC models of IP increases, designers are examining how to minimize modeling effort. This article addresses model development requirements and a software-driven verification method to reduce development time while increasing IP quality as an end result.
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Technical White Papers
- Shrinking SoC Design Cycles using DesignWare IP – a case study by STMicroelectronics
This paper discusses how St Microelectronics was able to significantly reduce the design cycle for an SoC that contains more than 10 million gates and had more than 15 complex communication and protocol interfaces.
Download Now - Protect Your Electronic Wallet Against Hackers: Securing critical data in consumer and multimedia mobile devices with NFC technology using Non-volatile Memory IP
This paper will help system architects and SoC designers gain familiarity with the options and tradeoffs of the various NVM IP on the market today in order to make the right selection, ensuring the maximum security of their system data.
Download Now - Unleash the Performance Benefits of Sigma-Delta ADCs into Your SoC: IP supports cellular communications, sensors and measurement markets
This paper will give SoC designers a clear understanding of the workings inside sigma-delta ADCs and explains when they are a better alternative than other ADC architectures that are used in advanced, deep sub-micron SoCs.
Download Now - Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP
This paper describes the power versus resolution trade-offs existing in the design of pipeline ADCs. It will also discuss how digital gain calibration eases those trade-offs, thus achieving significant improvements in power and area.
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Webinars
Industry Articles
Highlighted Videos
News
- Synopsys Awarded TSMC's Interface IP Partner of the Year- Technology Leadership and Outstanding Customer Support Cited as Key Selection Criteria
Learn more - Synopsys' DesignWare Audio IP Achieves First-Pass Silicon Success in Leading 65-nm and 55-nm Process Technologies - High-performance, Low Power DesignWare 96 dB Hi-Fi Audio IP Optimized for Mobile Multimedia and Digital Home SoC Applications
Learn more - UMC and Synopsys Collaborate to Develop DesignWare IP for 28-nanometer Technology - Collaboration on Embedded Memory and Logic Library for UMC's Enhanced Poly SiON HLP Process Enables Creation of High-Performance, Low-Power SoCs
Learn more - Synopsys' DesignWare SuperSpeed USB 3.0 IP Achieves More Than 40 Design Wins - Selected by More Than 30 Customers, Silicon-Proven USB 3.0 IP Lowers Integration Risk
Learn more - Synopsys' DesignWare STAR Memory System Shipped in 1 Billion Chips - Design Teams Worldwide Quickly Achieve Test and Repair Quality Goals for Embedded Memories
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