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Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing
Please join us for an in-depth technical webinar focused on new capabilities in DFTMAX™ compression and TetraMAX® ATPG that efficiently manage tester power and screen hard-to-detect defects. Register NOW!
Arif Samad, Group Director R&D; Adam Cron, Principal Engineer for Test Automation
Successful Equivalence Checking of Highly Optimized DC Ultra Designs
Please join us for an in-depth technical webinar focused on how to achieve successful verification on high performance designs compiled with DC Ultra.
Mitchell Mliner
Accelerate your design closure with DC Ultra
Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma & Janet Olson
Seminar Series 2009
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Webinars
View our online webinars and learn from technology experts on a variety of topics.
SNUG Conferences
Forum for Synopsys users to exchange, discuss and explore ideas
Workshop Series 2009
Hands-on learning from Synopsys experts
News
Digital Imaging Systems Achieves First-pass Silicon Success With Synopsys Galaxy Custom Designer
Synopsys and King Abdulaziz City of Science and Technology (KACST) Sign Agreement to Promote Knowledge-Based Society in Saudi Arabia
Synopsys Announces Earnings Release Date and Conference Call for Fourth Quarter and Fiscal Year 2009
Synopsys Chosen by Realtek as Its Primary EDA Partner
Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics
Media Advisory/Alert: Synopsys EDA Interoperability Forum to Feature Subodh Bapat Keynote on Green Computing
Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test
Juniper Chooses Synopsys as Its Primary EDA Partner
Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes
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Blogs
Low Power Blog: Magic Blue Smoke
A View from the Top: A System-Level Blog
AMS Verification Blog: Analog Insights
On Verification: A Software-to-Silicon Verification Blog
Standards Blog: The Standards Game
USB IP Blog: To USB or Not to USB
The Eyes Have it: An IP Blog
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Webinars
Simulation of Advanced Semiconductor Devices Including High-k/Metal-gate Transistors and FinFETs
The Recipe for Successful Formal Verification: Proper Constraining of Your Design
StarRC Custom Extraction for Custom IC Design
Automotive Electronics Reliability: A Software to Silicon Methodology
HSPICE/Custom Designer for Analog & RF Circuit Design
Front-to-Back AMS Flow using Custom Designer
Stratix-based Algorithm Acceleration Prototyping
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Events
SDR’09 (Software Defined Radio)
IP/ESC'09 (Embedded Systems Conference)
IEDM (International Electron Devices Meeting)
EMLC (European Mask & Lithography Conference)
DesignCon 2010
SPIE Advanced Lithography
DVCon 2010
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