The widespread use of custom circuits in today’s advanced system-on-chip designs is creating a severe design and simulation bottleneck. Increasing complexity combined with the modeling of new parasitic effects are exacerbating the accuracy concerns as well as resulting in 2-4x increase in simulation runtimes. In this webinar, our experts will explain how StarRC Custom’s unique solution enables high accuracy and optimized extraction for improved simulation throughput. Technologies that will be demonstrated include unified 3D field solver, context-specific MOS device parasitic extraction, CustomSim simulation efficiency links and OpenAccess based integration with the Galaxy Custom Designer implementation solution. November 11, 2009.
Baribrata Biswas, Group Director, R&D / Extraction , Synopsys Inc.; Omar Shah, CAE / Extraction, Synopsys Inc.

Star-RCXT™ provides unique gate-level extraction techniques to address productivity bottlenecks in physical implementation and signoff. Our experts demonstrate how the latest process modeling and extraction features can help you achieve accurate and faster signoff.
Krishnakumar Sundaresan, Principal Engineer at Synopsys; Hong Liu, CAE for extraction products at Synopsys