Hear a brief overview on low power design requirements for long running circuits and learn about an innovative approach to reduce the energy consumption of these circuits by selecting low power architectures, operand encoding and cell mappings based on power costing and switching activity considerations. Finally, get a brief introduction to the DesignWare® minPower Components and the additional power savings you can achieve on top of your current low power design methodology.
Synopsys

Consumers are demanding higher bandwidth for faster data transfer of video, pictures and music for the next generation of consumer electronic applications such as storage devices, camcorders, digital media players and smartphones. To address this demand, the new USB 3.0 (aka SuperSpeed USB) standard operates at 5Gbps and delivers more than 10x the bandwidth of USB 2.0, enabling faster "sync-and-go" functionality between PCs and portable electronic devices.
Synopsys

This webinar will discuss the necessary tasks of both the IP developer and integrator to ensure a fully functional SoC. It will explain how the high performance DesignWare Mixed-Signal PHY IP addresses issues such as jitter, robustness, power, testability and PVT invariance and provide insights on how to ensure high yield across process corners and manufacturing variations. Take this opportunity to learn about a built-in self test feature, which enables at-speed analog testing on a pure digital tester.
Synopsys

With today's increasingly complex SoC designs and constant pressure to reduce time to market, designers are turning to IP-based methodologies to solve their design challenges. AMBA® has become an important standard for today's SoCs by enabling designers to utilize IP-based methodologies at the subsystem level. This technical webcast presents how the Synopsys DesignWare® AMBA On-Chip Bus solution improves productivity during the design and verification of AMBA-based SoCs. Special emphasis will be placed on how DesignWare AMBA Verification IP, leverages OpenVera™ to provide advanced verification methodologies, which improve the quality of your design while reducing the overall verification time.
Synopsys

Virtualization technology has been used in high-end servers for quite some time. The evolution of virtualization has brought with it the desire to reduce the S/W overhead portion of virtualization, particularly for I/O devices. In this webinar: discover the different types of I/O Virtualization, learn how I/O Virtualization is addressed within the PCI Express® specification and understand the specific changes required to add I/O Virtualization to an existing PCI Express interface while providing an efficient, scalable I/O sharing solution that is compliant to the new stand.
Synopsys

Each memory transaction requires that signaling must meet set up and hold requirements for a given frequency. In fact, there are several timing domains that must be satisfied for each transaction. Each interface is source-synchronous, requiring the strict maintenance of skew and other uncertainty effects. For each of these interfaces, the contributors can be assigned to: the transmitter, the interconnect and the receiver. This webinar will discuss the impact of these sets of contributors, with emphasis on signal integrity techniques to address margin eroders such as crosstalk, simultaneously switching outputs, impedance mismatch and inter-symbol interference.
Synopsys

This webinar will outline critical areas to consider for the lowest power DDR interface including where power is consumed in embedded DDR systems, DDR3 vs. DDR2 power, correcting the "JEDEC-ophile" DDR misconceptions, PCs use DIMMs, SoCs use components (and sometimes DIMMs). It will also touch on how to select the optimal driver and ODT impedances for your system for Writes and Reads. The webinar will close with other power related issues and a brief introduction to Synopsys DesignWare® IP for DDR3/2 PHYs and Controllers.
Synopsys

This webinar will outline and discuss common misconceptions of the DRAM market including the realistic commodity DRAM roadmap for DDR2, DDR3 & LPDDR products (including how the speed grades get rolled out). It will discuss how the PC market drives the DRAM market and your SoC needs follow in the wake and when you should consider DDR2, DDR3 or LPDDR. Remember: Speed matters! Power matters! Size matters! Width matters! Price matters! Lastly the webinar will touch on how memory controllers cannot be built to DRAM standards and how the DRAM interface can affect your SoC design & package criteria.
Synopsys

In this webinar, you will learn how to utilize the new DesignWare® SATA Device IP core to implement the SATA interface into these types of mass storage devices and come to understand how the IP offers a flexible feature set and architecture, enables you to achieve your performance goals, while maintaining low power consumption for the overall system.
Synopsys

In this webinar discover how to take advantage of the constrained random verification approach and work through the challenges and learn how to successfully implement the key features that are necessary to build a constrained random verification environment. See the step by step methods and techniques for using DesignWare Verification IP in conjunction with Synopsys' proven VMM Methodology Standard Library for SystemVerilog to develop a robust verification environment, some of which include: Configuring, connecting and instantiating the Verification IP, simple directed and random tests, functional coverage, message control, connecting scoreboards.
Synopsys

In this webinar learn how to accurately calculate the internal FIFO size for the target Ethernet application and see how an IP core can easily be configured for different on-chip interfaces and applications. Learn how to include an Ethernet design into a reusable processor independent subsystem using the DesignWare IP for AMBA in conjunction with the Ethernet IP and get introduced to the Synopsys DesignWare Gigabit Ethernet IP solution, including multiple PHY interfaces.
Synopsys

Get introduced to the Synopsys DesignWare® IP for SATA AHCI Host, which supports the latest 2.6 SATA specification and is developed to meet the needs of existing and future designs for high performance and low power applications. Learn about the configuration of embedded DMA used to enhance performance, and the AHCI enabled Physical Region Descriptor feature used to offload CPU tasks. See how a single host IP core can be configured to support multiple SATA devices while maintaining high performance across all devices and finish up with a review of the SATA-specified power management features and the optional configurations which enable ultra low power consumption.
Synopsys

DDR2 SDRAM is an increasingly common memory solution for designs because of its price, availability, bandwidth capability, and wide range of configurations. However, the benefits of DDR2 SDRAM are coupled with significant implementation challenges at higher speed as the bit period shrinks and physical signaling issues become prominent. To further compound the problem, designers who use third-party IP as building blocks cannot assume interoperability among individual subsystem components. This session provides an overview to the memory interface subsystem design approach Synopsys proposes and how a complete integrated solution can reduce risk and increase design quality.
Synopsys

The move to integrated high-speed serial interfaces such as PCI Express, SATA and XAUI has brought new challenges in terms of production testing. The goal is to test these mixed-signal serial links with maximum fault coverage while utilizing the minimum amount of test time. The conventional approach using simple "external loop-back" are fast but not accurate, while expensive, sophisticated mixed-signal testers burden the user with additional overhead costs and having to write and debug complex test programs. To address this challenge, this webinar will show how Synopsys has implemented a built-in test solution for its DesignWare® PCIe®, SATA and XAUI PHY IP, where at-speed analog test can be done on a pure digital tester running at 10 MHz. This enables the user to generate verified pure digital test patterns for the all the important compliance tests and more, including eyemask, asynchronous voltage margining and transmit level testing. These tests can be generated by the user in less than 5 minutes with little no knowledge of the high-speed link - all with a push of a button. Using this capability, customers have gone from 1st silicon to production test in under two weeks.
Synopsys

Are you ready to integrate high-speed USB IP into your SoCs? With over 1500 successful USB tape-outs ranging from 0.35 micron down to 65 nm processes, Synopsys has identified key considerations that will help you seamlessly integrate the digital controller and PHY IP into your design. By using application examples and customer case studies from companies such as Open-Silicon, this discussion will cover system software, protocol, and PHY integration issues common to USB implementation for today's ultra-low power and cost sensitive designs. Understand how the next five years of USB designs will be shaped by consumer and technology demands for 45nm process and next generation USB standards.
Synopsys

How do you design and verify a subsystem using the AMBA 3 AXI protocol with the least amount of effort and in the shortest amount of time? An ARM11 processor-based platform, combined with ARM PrimeCell peripherals and Synopsys DesignWare Verification IP, delivers a standard framework for the efficient creation and validation of these high performance subsystems. In this seminar, you will learn about the ARM PrimeCell infrastructure and how the DesignWare Verification IP enables the development of a more thorough and reusable verification environment. The DesignWare Verification IP uses advanced verification methodologies such as a coverage driven constrained random verification process to quickly identify subsystem anomalies.
Synopsys

The AMBA 3 AXI bus protocol is the newest and most capable on-chip fabric protocol introduced by ARM, delivering scalable performance, configurable to customers bandwidth/speed/area/power requirements. Designers and verification engineers using this protocol are faced with a unique set of challenges to both subsystem design and validation. We will identify a number of the challenges faced in verifying AMBA 3 AXI bus protocol based design. We will then show how you can address these challenges and accelerate your verification process with the DesignWare Verification IP for AMBA 3 AXI which supports the Verification Methodology Manual (VMM) defined xVC verification layer. The presentation includes a technical explanation of the xVC layer and how the Synopsys DesignWare Verification IP can be used to re-run ARM supplied xVC based IP validation tests.
Synopsys

This webinar focuses on the challenges, and solutions, of one of the significant growth areas for third party IP namely high speed serial interconnects such as PCI Express, SATA and XAUI. At operating speeds of 2.5 Gb/s and higher on a standard printed circuit board, many challenges arise, for example isolating manufacturing defects such as transmission line loss, impedance discontinuities and crosstalk. But these are just some of the challenges. Others include verification, chip integration of third party IP, built-in test capabilities, ESD, yield across manufacturing variations, meeting overall jitter/power budgets and bit error rate specifications. And finally, production testing of high speed serial interconnects is very difficult and a solution to this problem using on-chip ATE will be presented.
Synopsys

The AMBA 3 AXI bus protocol is the newest on-chip bus protocol introduced by ARM. Designers and verification engineers using this protocol are faced with a unique set of challenges when verifying their designs. We will identify the key challenges faced in verifying AMBA 3 AXI bus protocol based design. We will then show how you can address these challenges and accelerate your verification process by using DesignWare VIP for AMBA 3 AXI and Reference Verification Methodology. Also covered is an overview of the AMBA 3 AXI bus protocol and how it differs from AMBA 2 AHB.
Synopsys

Recent design start trends in consumer electronics, wireless applications, and networking devices are requiring an increasing amount of datapath content. Regardless of the datapath circuit size, managing performance is very critical to meeting the overall design target. In this session, we will provide insights into one of most popular features of DC Ultra and discuss how the best-in-class datapath technology from DC Ultra and DesignWare Library helps produce the best synthesis quality of results (QoR).
Synopsys

First in a series of webcasts from Synopsys, this presentation will review some of the complex features of PCI Express and the economics of adding the interface to your designs. Follow on webcasts will cover PCI Express system level design issues and achieving compliance for your products.
Synopsys