Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The latest extraction features in Star-RCXT can enable up to 10x speed-up in simulation runtime while preserving golden accuracy. In this webinar our experts will explain innovative techniques, such as "context-specific" and "active-node" based extraction, to boost simulation performance and capacity for your custom digital, memory or AMS designs.
Synopsys

In this webinar you will learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement. Increase design confidence by finding electrical rule violations and power management failures rapidly with a comprehensive set of static and dynamic native circuit checks.
Synopsys

Over the past few years, Synopsys has sped up HSPICE, achieving industry leading performance while maintaining HSPICE’s “signoff quality” simulation accuracy.
Dr. Kishore Singhal, Synopsys Scientist, Dr. Scott Wedge, Sr. Staff Engineer, Ted Mido, Sr. Staff Engineer, Harald Von Sosen – Principle Engineer

For years designers around the world have trusted HSPICE for their signal integrity simulation needs.
Dr. Scott Wedge Senior Staff Engineer, Synopsys Ted Mido Senior Staff Engineer

Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design.
Dr. Scott Wedge Senior Staff Engineer, Synopsys

Fast-SPICE simulation used to be limited primarily to functional verification, but no more!
Synopsys