This webinar will discuss the application of TCAD to high-k/metal-gate transistors and 3-D modeling FinFET devices, focusing on the physical models and 3-D modeling techniques required to achieve successful simulations.
Synopsys, Inc.
Dec 01, 2009

Increasingly, verification engineers are deploying formal verification tools with simulation to solve today’s toughest verification problems. Properly constraining your design can mean the difference between success and failure when deploying formal tools. In this webinar, you will learn all about constraints and how their proper specification and use will help you quickly achieve your verification goals. We will also highlight some of the unique features of Synopsys’ Magellan hybrid formal tool that help detect and debug over-constraining of your formal setup, thereby increasing your confidence in your formal verification results. Following the technical presentation, an interactive Q&A session with a panel of Synopsys verification experts will take place.
Krishna Balachandran, Director of Marketing, Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; and Dan Benua, Principal Engineer, Synopsys
Nov 11, 2009

The widespread use of custom circuits in today’s advanced system-on-chip designs is creating a severe design and simulation bottleneck. Increasing complexity combined with the modeling of new parasitic effects are exacerbating the accuracy concerns as well as resulting in 2-4x increase in simulation runtimes. In this webinar, our experts will explain how StarRC Custom’s unique solution enables high accuracy and optimized extraction for improved simulation throughput. Technologies that will be demonstrated include unified 3D field solver, context-specific MOS device parasitic extraction, CustomSim simulation efficiency links and OpenAccess based integration with the Galaxy Custom Designer implementation solution. November 11, 2009.
Baribrata Biswas, Group Director, R&D / Extraction , Synopsys Inc.; Omar Shah, CAE / Extraction, Synopsys Inc.
Nov 11, 2009

Designers of automotive ICs and systems must manage a number of key problems; harsh operating conditions, a rapid rise in the amount and complexity of software, increasingly complex HW/SW interaction, and the need to ensure the manufacturability of IC designs. This webinar addresses the use of Synopsys "Software to Silicon Methodology" in analyzing, designing, and verifying designs that will result in the highest quality automotive ICs, components, and systems.
Anthony Stone
Nov 10, 2009

Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, and Fredrik Ivarsson, Custom Design Corporate Applications Engineer
Nov 04, 2009

Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, and Chris Shaw, Technical Marketing Manager
Nov 03, 2009

This webcast will discuss how the unique features of Altera's high-end Stratix-FPGAs when combined with Synopsys high-performance rapid protoyping solutions enable new use modes and capabilities for algorithmic acceleration, as well as for highest performance rapid prototyping. These systems are widely used as a way to shorten development time, start software development earlier in the design cycle and reduce the risk of design respins. Whether you're doing system validation, pre-silicon development, or system level algorithmic design, Stratix-based prototyping platforms deliver unique capabilities, and provide a high-level of confidence to meet demanding time-to-market needs.
Synopsys
Oct 29, 2009

In this webinar, you will learn how VCS multicore technology allows users to reduce verification time for long-running tests by leveraging their multicore computing infrastructure. We will cover VCS multicore technology’s two flexible use models – application-level parallelism (ALP), which allows users to simultaneously simulate assertions, coverage and plotting concurrently on multiple cores, and design-level parallelism (DLP), which enables the concurrent simulation of multiple instances of a core, several partitions of a large design or an optimized combination of both. Following the detailed technical presentation, an interactive Q&A session with our panel of experts will take place.
Chiang, Product Marketing Manager, Synopsys; Usha Gaira, Corporate Applications Engineer, Synopsys; Amitabh Chand, Corporate Applications Engineering Manager, Synopsys; and Jatinder Goraya, Research and Development Engineer, Synopsys
Oct 27, 2009

Can hardware and software be developed for SoCs independently, or are the two so tightly coupled they must be developed concurrently? Can modeling the "system" wait until actual silicon is available, or must it be done with better tools at the architecture stage before the SoC is created?
Synopsys, Mentor and Cadence
Oct 14, 2009

VMM is the most widely adopted and proven verification methodology in the industry, with production-deployment on over 500 projects, tens of millions of lines of user code and more than 50 published user papers. VMM base classes, VMM Applications (such as RAL and Performance Analyzer) and VMM for Low Power (VMM-LP) are deployed worldwide to address the toughest verification challenges. In this webinar, you will learn about the latest developments in VMM. Our VMM experts will cover recent enhancements, including TLM 2.0 support, improved block-to-top reuse heirarchical phasing and several additional ease-of-use deployment features. Following the technical presentation an interactive Q&A session will take place.
Albert Chiang, Product Marketing Manager; Yassine Eben Amine, Applications Consultant; and Kiran Maiya, Senior Corporate Applications Engineer
Oct 13, 2009

The power consumed by electronic devices has been on a downward path for many years as a result of the hard work and creativity of talented engineers. This course looks at the fundamentals of achieving the low power operation needed with nearly all of today's leading-edge chip designs.
Synopsys Inc.
Oct 01, 2009

There is a thriving ecosystem around IC Compiler and the Galaxy Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity by attending this free webinar.
JC Lin
Sep 30, 2009

Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The latest extraction features in Star-RCXT can enable up to 10x speed-up in simulation runtime while preserving golden accuracy. In this webinar our experts will explain innovative techniques, such as "context-specific" and "active-node" based extraction, to boost simulation performance and capacity for your custom digital, memory or AMS designs.
Synopsys
Sep 22, 2009

Hear a brief overview on low power design requirements for long running circuits and learn about an innovative approach to reduce the energy consumption of these circuits by selecting low power architectures, operand encoding and cell mappings based on power costing and switching activity considerations. Finally, get a brief introduction to the DesignWare® minPower Components and the additional power savings you can achieve on top of your current low power design methodology.
Synopsys
Sep 22, 2009

Learn about Synopsys’ comprehensive software-to-silicon verification solution for early software development & architectural exploration. Visit the archived virtual conference to browse demos, white papers and other material and listen to Synopsys’ two panels addressing key SoC development challenges.
Synopsys
Sep 16, 2009

Achieving complete verification of today's complex designs is, at best, a difficult and time consuming task that requires a combination of verification technologies. Design/verification teams use formal techniques to exhaustively prove functionality of small blocks, while resorting to simulation for full-chip verification. One of the barriers to using formal techniques has been the difficulty in leveraging an existing simulation environment. It has also been difficult to correlate the coverage information from formal tools with that from simulation. In this webinar, you will learn how Synopsys' Magellan seamlessly integrates formal verification with simulation to remove these barriers.
Krishna Balachandran, Director of Verifiation Marketing; Xiaolin Chen, Corporate Applications Engineer; Mandar Munishwar Corporate Applications Engineer; Dan Benua, Principal Engineer
Sep 09, 2009

The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we focus first on the complexities and changes brought about in the low power era and the bug types that are new to low power design. We then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar highlights the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs.
Krishna Balachandran, Director of Low Power Verification Marketing; Srikanth Jadcherla, Group Director of R&D and Janick Bergeron, Synopsys Fellow
Aug 11, 2009

With recent mandates on idle energy requirements for household electronic appliances, low power design has moved from the domain of handhelds and mobile electronics to plugged-in-the-wall devices. An understanding of the impact on verification arising from the deployment of low power design techniques is the key to successful verification. In this webinar, you will learn why verification has fundamentally changed for low power designs and how Synopsys' VCS with MVSIM and MVRC comprehensively and accurately meet the verification challenges. You will also hear about how these tools embody the principles outlined in the recently published Verification Methodology Manual for Low Power (VMM-LP).
Krishna Balachandran, Director of Low Power Verification Marketing and Prapanna Tiwari, Corporate Applications Engineering Manager
Aug 11, 2009

Please join us for an in-depth technical webinar focused on new capabilities in DFTMAX™ compression and TetraMAX® ATPG that efficiently manage tester power and screen hard-to-detect defects. Register NOW!
Arif Samad, Group Director R&D; Adam Cron, Principal Engineer for Test Automation
Aug 05, 2009

Consumers are demanding higher bandwidth for faster data transfer of video, pictures and music for the next generation of consumer electronic applications such as storage devices, camcorders, digital media players and smartphones. To address this demand, the new USB 3.0 (aka SuperSpeed USB) standard operates at 5Gbps and delivers more than 10x the bandwidth of USB 2.0, enabling faster "sync-and-go" functionality between PCs and portable electronic devices.
Synopsys
Jul 22, 2009

Star-RCXT™ provides unique gate-level extraction techniques to address productivity bottlenecks in physical implementation and signoff. Our experts demonstrate how the latest process modeling and extraction features can help you achieve accurate and faster signoff.
Krishnakumar Sundaresan, Principal Engineer at Synopsys; Hong Liu, CAE for extraction products at Synopsys
Jul 21, 2009

Predicting the future is a hazardous endeavor, but tracking trends can at least provide a glimpse of what is to come. A key trend in embedded systems is the increasing need for reduced power consumption, which is driven by demand for portable devices, higher energy costs and environmental pressures. The role of embedded software and real time operating systems in delivering power reductions on target embedded hardware is not obvious. In this session the key factors will be reviewed in detail.
Synopsys and Mentor Graphics
Jul 15, 2009

This EE Times virtual conference focused on multicore which is one of the biggest challenges design engineers currently face which is deciding when to adopt multicore processors in their designs and what implications that has for the software tools they will need to use. Visit the Synopsys booth to learn how virtual platforms can solve your multicore software development challenges, download the whitepapers and webinars.
Synopsys
Jun 18, 2009

Multicore hardware is the easy part; where do the development tools come from? In this webinar we’ll meet the tool makers that are tackling these problems and see what treasures and hurdles await the designer.
Synopsys, Wind River, CriticalBlue, MontaVista
Jun 18, 2009

Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma & Janet Olson
Jun 12, 2009