The ongoing technology scaling provides improved area, cost, speed, leakage, and power. We look at the technology innovations that are necessary to go from the current 32nm node to the next (22nm) node and beyond. For the last 40 years, semiconductor industry has been driven by planar MOSFETs, which are expected to be still manufactured at 22nm node, but will be initially complemented, and eventually overtaken by alternative transistor architectures. We review the alternative transistor architectures and the differences in their inherent variability mechanisms. Special attention is devoted to the analysis of performance boosting high-k/metal gate and stress engineering technologies and how they can be used to leverage either speed or leakage or both. In addition to conventional layout scaling that doubles transistor density for each subsequent technology node, 3D chip integration using through-silicon vias (TSV) is expected to be in high volume production within the next two years. We present TSV process flow and TSV impact on the adjacent circuit.
Dr. Victor Moroz, Synopsys

Transistor scaling has yielded continual improvements in integrated-circuit performance and cost per function over the past several decades, ushering in the Information Age. Continued transistor scaling will not be as straightforward in the future as it has been in the past, however, due to fundamental limits leading to increased power consumption. In this seminar, we will discuss recent developments, research, and challenges in micro-relay technology and circuits that aim to overcome the CMOS power crisis and usher in the Age of Ambient Intelligence.
Professor Tsu-Jae King Liu & Professor Elad Alon, UC Berkeley

This talk provides an overview of various 3D IC research projects being conducted at the Georgia Tech Computer-Aided Design (GTCAD) Laboratory. With the support of the US National Security Agency (NSA), we are currently building a many-core 3D processor with stacked memory (arguably the first in academia). Our 3D processor features 64 cores and SRAM memory banks that are interconnected with high-density through-silicon-vias (TSV).
Sung Kyu Lim, Georgia Institute of Technology

Direct numerical simulation has become one of few available means for the systematic study of physical or artificial processes for which experiments are expensive and/or time-consuming to perform. But without the aid of systematic strategies for reducing model complexity, the burdens of complex geometries, multi-physics, and operating environments coupled with an ever increasing appetite for accuracy and model fidelity, would likely render simulation an ineffective tool. In this talk we will give an overview of projection methods for model reduction and discuss some recent results.
Thanos Antoulas, Rice University

The areas chosen for this tutorial include wireless, automotive, IP, and EDA flows. A general overview of low power design and verification challenges for SoC designers will set the context for each of the application areas.
Yatin Trivedi¹, Gary Delp², John Biggs³, Srikanth Jadcherla¹, Synopsys Inc.¹, LSI², ARM³

Verification consumes continue to consume the majority of the implementation effort of any new design. In an era of billion-gate chips, ultra-low power and consumer-driven economics, how can we continue to deliver working designs at an acceptable cost?
Janick Bergeron, Synopsys Inc.

Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single chip. However, scaling is facing several problems – severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. We believe that device aware circuit and architecture design along with statistical design techniques can provide large improvement in power dissipation (Vdd scaling) while providing the required reliability and yield. In this talk design techniques to address power and reliability problems in scaled technologies for both logic and memories will be presented.
Kaushik Roy, Purdue University

The Semiconductor Research Corporation and National Science Foundation have joined together in a new initiative to improve multi-core computer chips for advancing semiconductor performance.
Bill Joyner, Sankar Basu, Semiconductor Research Corporation, National Science Foundation

In this tutorial, we discuss how to choose design features that are candidates for verification using simulation, assertion-based verification and formal analysis so that the overall verification labor is minimized while verification completeness is maximized.
Shankar Hemmady and Badri Gopalan, Synopsys Inc.

In this tutorial, we look into the details of some of the key power management techniques that leverage voltage as a handle: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). We look into their verification and testing implications.
Bhanu Kapoor¹, Shankar Hemmady², Shireesh Verma³, Kaushik Roy⁴, Mimasic¹, Synopsys Inc.², Conexant Systems³, Purdue University⁴

In this presentation, we will discuss the sources of process variability, their impact on design layouts, and how to manage process variability to improve design quality.
Terry Ma, Synopsys Inc.

In this tutorial, we focus on circuit/architectural design techniques for low power under parameter variations. We consider both logic and memory design and encompass modeling, analysis as well as design methodology to simultaneously achieve low power and variation tolerance. Design techniques to minimize power under parametric yield constraint as well as major process adaptation techniques using voltage scaling, adaptive body biasing or logic restructuring will be presented. Techniques to deal with within-die parameter variations in logic and memory circuits primarily caused by random dopant fluctuations will be discussed. Finally, we will discuss temperature-aware design, dynamic adaptation to temperature and on-going research activities on low-power and variation tolerant multi-core processor design.
Swarup Bhunia, Case Western Reserve University

In the first part of the talk, we will present process variation induced failures (read, write, access, hold) in 6T cells and introduce various self-tuning and self-healing schemes to improve memory yield in scaled technologies. Other bitcell configurations for improved memory stability with high dynamic range (supply voltage) will also be presented. In the second part of the talk, we will consider double gate technologies such as FinFETs and technology/circuit co-design for SRAMs.
Kaushik Roy, Purdue University

In this tutorial, we look at some of the challenges of physical access layer validation and discuss how SystemVerilog testbench constructs can be used to create random yet valid frames for WiMAX OFDMA to validate the physical access layer protocols.
Albert Chiang¹, Wei-Hua Han¹, Bhanu Kappor² , Synopsys Inc.¹, Mimasic²

It now appears to be a manifest destiny that multiprocessors will displace uniprocessors as the general-purpose computing platform for future desktop computers, laptop computers, and even cellular handsets. This talk will outline perspectives on a number of attendant trends that form "the Berkeley View."
Professor Kurt Keutzer, EECS University of California Berkeley

Many approaches have been introduced to address the concerns regarding both active and standby power. Yet, none of these provides a persistent answer that extends into the foreseeable future. Going to the next step will require us to venture in some new directions, some of which may be quite unorthodox. In this presentation, we will browse some of the opportunities that may arise through ultra low-power design and outline some potential solutions.
Dr. Jan Rabaey Donald O. Pederson Distinguished Professor University of California Berkeley

This presentation will introduce some existing methodologies for designing ICs that are free of global clock distribution networks. These ICs have lower power and are less sensitive to variation compared to their conventional counterparts. Research opportunities for new tools in this area will also be addressed.
Dr. Robert Damiano, Former Synopsys Fellow and Vice President, Advanced Technology Group

In this presentation, Dr. Richard Newton introduces us to Bio Design Automation (BDA) or Synthetic Biology, the practice of assembling new living systems on a biological substrate to perform a specific function. A new field which has the potential to revolutionize our world just as microelectronics has done in our lifetime.
Dr. A. Richard Newton, Late Dean and Roy W. Carlson Professor of Engineering University of California, Berkeley

There are two great truths in design: If it's not tested, it's broken. And if it's not simple, it's broken. This talk focuses on aspects of both issues as it applies to software code development.
Mike Keating, Synopsys Fellow

In this presentation, Dr. Richard Newton presents two major advanced research activities underway at Berkeley and at other major research centers that promise to close that gap: the first at the materials level and second at the system level.
Dr. A. Richard Newton, Late Dean and the Roy W. Carlson Professor of Engineering University of California, Berkeley