Over the last 25 years, there have been two major revolutions in how we do digital design: the move to language/synthesis based design (starting in 1986) and design reuse (starting around 1996). We are well overdue for a third revolution. Current design methods are not meeting the needs dictated by the complexity and size of today’s SoC designs, much less the designs of the future. This talk will describe the current candidates for the next revolution in digital design: high level synthesis, chip generators, and radical extensions to the synthesizable subset of current RTL languages. It will also describe how the economics of SoC design and manufacturing, as well as the economics of EDA, will affect and possibly de-rail the third revolution.
Mike Keating, Synopsys Inc.

Due to changing product requirements, our group recently rewrote the Raphael-NXT random walk capacitance extraction product. Surprisingly good results were obtained, a 20X improvement in speed, a 3X reduction in memory and 6X reduction in lines of code at the same level of accuracy. These improvements were due to both changes in the numeric algorithms and changes in software architecture goals. After an introduction to random walk capacitance extraction the presentation will discuss how problem areas were identified and the performance improvement was made possible.
Dr. Greg Rollins, Synopsys

Design is so expensive we can’t afford to spend it on creating a single chip. Working out the interactions in a complex design is challenging and costs a lot of money, even when we do it well. The key is to leverage this work over a broader range of chips – we need to design chip-generators and not chips. One creates a virtual programmable chip (the generator) that is MUCH more flexible than any real chip (it has no resource constraints) and the application designer (the new chip designer) then configures this system to produce a customized chip at low cost. While there are many hard problems that need to be addressed to make this work, none seem insurmountable. I will present some recent examples from my group which indicate the promise of this approach - including improving the energy efficiency of a H.264 encoder by 200x, and validating a chip generator.
Mark Horowitz, Stanford University

Software and Functional Verification are the two largest and fastest-growing components of chip design cost. They are also the aspects of chip design that involve large – or even huge – amounts of code. The languages used in chip design – SystemVerilog, C++ - allow the creation of very complex functionality, and semiconductor technology and EDA tools allow us to implement these complex designs. But our approach to code-based design has not enabled us to manage this complexity effectively. In particular, newly graduated students do not have the tools or the theoretical grounding to develop code-based designs that will meet the needs of the chips of the next decade – when we may well see chips with 1 trillion transistors. This talk will outline the nature of the challenges of code-based design and suggest a path for managing the functional complexity demanded – and enabled – by tomorrow’s SoC designs.
Mike Keating, Synopsys Inc.

3D stacking and integration with TSVs can provide significant system advantages in terms of power, scale, cost and performance. This talk will cover what we have learned at NCSU over the past five years putting together CAD flows for 3DIC design and designing multiple 3DIC chips in the Lincoln Labs and Tezzaron 3D processes. Issues to be covered in detail include 3D motivation, system engineering, floorplanning and partitioning, thermal analaysis and CAD flow.
Prof. Paul Franzon, North Carolina State University

Our research group has been working on logic synthesis with forays into formal verification for several decades. As a result, we have become increasingly aware of the similarity between these two lines of research, resulting in a synergistic approach, which is our main research focus these days. For example, formal verification systems often use And-Invertor-Graphs (AIGs). Verification experts developed these and came up with very fast methods to reduce the AIG representation for use in verification engines. Recently, these computations have been extended to work in synthesis, resulting in improved quality and scalability, as exemplified by its successful adoption in several FPGA synthesis tools. Investigation of the commonalities between logic synthesis and formal verification led us to develop a new CAD tool, ABC, which is both a synthesis and verification tool. ABC is a public domain system in development at Berkeley. It has become popular with academic institutions as well as industrial companies. In the talk, ABC will be overviewed and some of the synthesis techniques borrowed from verification will be described.
Prof. Robert K. Brayton and Prof. Alan Mishchenko, University of California Berkeley

This paper analyzes the effectiveness of the use of thermal TSVs in lowering the overall average temperature of a 3D IC vertical stack as well as the impact and significance of thermal TSV count on the vertical and lateral thermal gradients in the stack for a given set of initial boundary conditions. A set of simulations were carried out using a 3DIC compact thermal model simulator on a multi-tier multi-die 3DIC design to access these effects of thermal TSVs.
Min Ni, Qing Su, Zongwu Tang, and Jamil Kawa, Synopsys Inc.

This tutorial addresses the multi-physics challenges associated with TSV based 3D IC technology that need to be considered including mechanical and thermal stresses experienced inter-die and intra-die and the impact of those stresses on performance and on reliability.
Jamil Kawa, Synopsys Inc.

Clock skew scheduling is a useful sequential circuit optimization method. The run time efficiency of this problem becomes crucial if it must be repeated iteratively in a higher level optimization. The widely recognized Burns' algorithm proposed to solve this problem suffers from high runtime complexity, which makes it unsuitable to be deployed in iterative optimization loops. This algorithm is based on the general concept of primal-dual optimization. In this paper, we demonstrate that a more efficient approach to the clock skew scheduling problem can be developed by designing a new algorithm using the same primal-dual optimization concept. The basic idea of the algorithm is to avoid creating new admissible graph and recalculating theta values for each iteration of the primal-dual optimization. The asymptotic runtime efficiency of our algorithm is of O(|V||E|+|V|log|V|), which is improved from O(|V|^2|E|) thanks to the heap data structure used in our proposed algorithm. The experimental results show that our algorithm is on average 95 times faster than Burns' implementation. In a best case, we can observe as much as 189 times speedup.
Min Ni¹ and Seda Ogrenci Memik², Synopsys Inc.¹, Northwestern University²

Traditional verification approaches for analog & mixed-signal designs do not scale well with increasing design complexity and product functionality. Full chip verification in the presence of analog components can be very slow, tedious, and difficult to maintain. In this tutorial, we focus on a scalable methodology for analog & mixed-signal verification that leverages advanced techniques used for verification of digital designs. Behavioral modeling using Verilog-AMS and SystemVerilog constructs will be presented. This tutorial addresses the several challenging issues that present road blocks for verification closure, and presents a methodology that promotes reuse and easy to maintain verification environment. Various strategies will be explored, for both top-down and bottom-up approaches, to develop a framework that can be shared across design teams, design stages, and product cycles.
Shyam Rapaka and Tapan Halder, Synopsys Inc.

With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively lower yields potentially undermine the profits of semiconductor companies across all industry segments. Embedding redundant logic into designs can improve product yields, but is this economically viable for most systems-on-chip? This paper attempts to answer this fundamental question. After describing an example architecture for built-in logic redundancy (BILR), we examine precisely how the BILR design and test parameters affect the area overhead, test execution time and yield of the redundant system. After conveying the cost model, we present analysis results showing that redundancy could be cost-effective, depending on a number of cost infrastructure variables that include the parameters of the BILR system itself.
Chris Allsup, Synopsys Inc.

Over the last 40 years, test has moved from being a fab tool to being a design tool, and has become an integral part of the design flow. This move has allowed better (QOR), cheaper (COR), and faster (TTR) test. As the vanguards of the semiconductor industry approach the 32-nanometer node and start planning the jump to the 22-nanometer node, a number of fundamental challenges are emerging, which force a thorough rethinking of the role of test. Like drugs, which often have counter-indications and side effects, even nanometer design and manufacturing are not immune to drawbacks. This requires that test assume an equal station to nanometer design and manufacturing, is accounted for by them, and inter-operates thoroughly with them. Both implementation and yield management tools may feed test with the design and manufacturing-related information it needs to keep problems manageable, while guaranteeing the desired quality and cost of results. At the same time, test can feed implementation and manufacturing with a great deal of information, which can help identify, locate, fix and/or prevent yield issues. In this keynote, Dr. Domic will describe how design, manufacturing, and test can join forces, and “collaborate” to battle the nanometer challenges.
Dr. Antun Domic, Synopsys Inc.

The photovoltaic industry is undergoing a transformational evolution as it expands production capacity and deployments to meet the growing need for green alternative sources of electricity production. Two of the primary drivers for the industry are the reduction in the cost of the solar cells and modules, and the improvement of the performance, particularly the conversion efficiency. To meet these challenges, new materials, manufacturing technologies and cell designs are being investigated. To support this development, simulation provides key insights into the physics of solar cell operation, enabling engineers to fully explore the range of design alternatives. At the module and system level, behavioral models allow engineers to examine design trade-offs which impact system performance. This talk reviews the current status of simulation in the development of photovoltaic technologies, from solar cell design to system performance, and provides an outlook for future work.
Ricardo Borges, Kurt Mueller, and Nelson Braga, Synopsys Inc.

The ongoing technology scaling provides improved area, cost, speed, leakage, and power. We look at the technology innovations that are necessary to go from the current 32nm node to the next (22nm) node and beyond. For the last 40 years, semiconductor industry has been driven by planar MOSFETs, which are expected to be still manufactured at 22nm node, but will be initially complemented, and eventually overtaken by alternative transistor architectures. We review the alternative transistor architectures and the differences in their inherent variability mechanisms. Special attention is devoted to the analysis of performance boosting high-k/metal gate and stress engineering technologies and how they can be used to leverage either speed or leakage or both. In addition to conventional layout scaling that doubles transistor density for each subsequent technology node, 3D chip integration using through-silicon vias (TSV) is expected to be in high volume production within the next two years. We present TSV process flow and TSV impact on the adjacent circuit.
Dr. Victor Moroz, Synopsys

Transistor scaling has yielded continual improvements in integrated-circuit performance and cost per function over the past several decades, ushering in the Information Age. Continued transistor scaling will not be as straightforward in the future as it has been in the past, however, due to fundamental limits leading to increased power consumption. In this seminar, we will discuss recent developments, research, and challenges in micro-relay technology and circuits that aim to overcome the CMOS power crisis and usher in the Age of Ambient Intelligence.
Professor Tsu-Jae King Liu & Professor Elad Alon, UC Berkeley

This talk provides an overview of various 3D IC research projects being conducted at the Georgia Tech Computer-Aided Design (GTCAD) Laboratory. With the support of the US National Security Agency (NSA), we are currently building a many-core 3D processor with stacked memory (arguably the first in academia). Our 3D processor features 64 cores and SRAM memory banks that are interconnected with high-density through-silicon-vias (TSV).
Sung Kyu Lim, Georgia Institute of Technology

Direct numerical simulation has become one of few available means for the systematic study of physical or artificial processes for which experiments are expensive and/or time-consuming to perform. But without the aid of systematic strategies for reducing model complexity, the burdens of complex geometries, multi-physics, and operating environments coupled with an ever increasing appetite for accuracy and model fidelity, would likely render simulation an ineffective tool. In this talk we will give an overview of projection methods for model reduction and discuss some recent results.
Thanos Antoulas, Rice University

The areas chosen for this tutorial include wireless, automotive, IP, and EDA flows. A general overview of low power design and verification challenges for SoC designers will set the context for each of the application areas.
Yatin Trivedi¹, Gary Delp², John Biggs³, Srikanth Jadcherla¹, Synopsys Inc.¹, LSI², ARM³

Verification consumes continue to consume the majority of the implementation effort of any new design. In an era of billion-gate chips, ultra-low power and consumer-driven economics, how can we continue to deliver working designs at an acceptable cost?
Janick Bergeron, Synopsys Inc.

Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single chip. However, scaling is facing several problems – severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. We believe that device aware circuit and architecture design along with statistical design techniques can provide large improvement in power dissipation (Vdd scaling) while providing the required reliability and yield. In this talk design techniques to address power and reliability problems in scaled technologies for both logic and memories will be presented.
Kaushik Roy, Purdue University

The Semiconductor Research Corporation and National Science Foundation have joined together in a new initiative to improve multi-core computer chips for advancing semiconductor performance.
Bill Joyner, Sankar Basu, Semiconductor Research Corporation, National Science Foundation

In this tutorial, we discuss how to choose design features that are candidates for verification using simulation, assertion-based verification and formal analysis so that the overall verification labor is minimized while verification completeness is maximized.
Shankar Hemmady and Badri Gopalan, Synopsys Inc.

In this tutorial, we look into the details of some of the key power management techniques that leverage voltage as a handle: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). We look into their verification and testing implications.
Bhanu Kapoor¹, Shankar Hemmady², Shireesh Verma³, Kaushik Roy⁴, Mimasic¹, Synopsys Inc.², Conexant Systems³, Purdue University⁴

In this presentation, we will discuss the sources of process variability, their impact on design layouts, and how to manage process variability to improve design quality.
Terry Ma, Synopsys Inc.