This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers.
Oct 27, 2009

This paper describes Haydn, a hardware compilation approach which aims to combine the benefits of cycle accurate descriptions such as ease of control and performance, and the rapid development and design exploration facilities in behavioral synthesis tools.
Oct 27, 2009

We have developed a full-custom IC design flow based on Synopsys custom design tools and the recently released Synopsys 90nm generic library. The developed design flow can be used for teaching VLSI and digital IC design courses.
Aug 24, 2009

An open Educational Design Kit (EDK) which supports a 90nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PCells.
Aug 24, 2009

Researchers at IIT Bombay have used Synopsys tools to facilitate research in Nanoelectronics, leading to publications in reputed international journals and conferences in recent years. The following areas are under active investigation.
Aug 24, 2009

These papers focus on the research, development, and application of design techniques & methods, design processes, and EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits.
Jun 17, 2009

In this paper, we demonstrate that by applying SVD to the original Abbe’s kernels, the essential kernels according to their singular values can be efficiently extracted. The experimental results our algorithm, the Abbe-SVD method, shows over 100X of both runtime and memory saving over traditional Hopkin’s SVD methods for kernel generation.
Jun 17, 2009

Eighteen months ago, we started the analysis of a mathematical problem which was selected as the target application for the first fully automated ASIC development of the IIIE (Instituto de Investigaciones en Ingeniería Eléctrica).
Apr 10, 2009

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters.
Mar 30, 2009

The top student projects from the Special Topics in Circuits and Signal Processing course at the University of California Los Angeles are presented in this article. These projects used Synplify DSP tools in a Matlab/Simulink environment to model designs and perform architecture design. Students did a range of projects including theoretical studies of quantization effects in digital filters, optimization of finite word-length effects and parallel data processing for neuroscience.
Feb 26, 2009

Faculty in the Electrical Engineering Department at the University of Washington use several Synopsys tools for studies on reconfigurable systems. Design Compiler has been used to create hardware blocks. Pathmill has been used for extracting timing information, testing several layout generation methods and final analysis of the results.
Feb 26, 2009

Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a high-level model of the memory, greatly aids simulation-based validation, but accurate scoreboards are complex to create since often they depend not only on the memory and consistency model but also on its specific implementation. This paper describes a methodology of using a relaxed scoreboard, which greatly reduces the complexity of creating these memory models.
Jan 08, 2009

Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital signal processing to enhance the performance analog building blocks has become an active research topic. In this work, we present a digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution A/D converters.
Jan 08, 2009

Eighteen months ago, we started the analysis of a mathematical problem which was selected as the target application for the first fully automated ASIC development of the IIIE (Instituto de Investigaciones en Ingeniería Eléctrica). The PWL (Piece Wise Linear) Function Computation problem was chosen because this kind of function allows the representation of n-dimensional non-linear functions in a convenient way for computing systems, and non-linear functions are of relevance in control systems, one of the most active areas at the IIIE.
Jan 08, 2009

Clarification of robustness for threshold voltage (Vth) variation in FinFETs is very important. Vth variation (delta-Vth) caused by fluctuations of some principal device parameters are evaluated, compared to the planar MOSFETs. However, the origin of delta-Vth is complex in short channel devices due to contribution of short channel effects (SCEs).
Dec 09, 2008

Continuous speech recognition enables people to talk at a normal speed and control their electronic world. Unfortunately, continuous speech recognition is a computationally intensive problem that exceeds the processing capability of high-performance processors.
Nov 17, 2008

Much has been written recently about the new opportunities structured ASICs offer designers seeking a highly integrated silicon solution for low- to mid-volume applications. This new architecture strikes an attractive middle ground between the high NRE costs and long development cycles associated with cell-based ASICs, and the performance limitations and higher unit costs of FPGAs.
Nov 17, 2008

As fuel costs continue to increase and questions arise regarding the future of our combustible resources, there has been renewed interest in electric and alternative fuel vehicles. Numerous automotive manufacturers are now sporting a range of hybrid vehicles and some are pursuing research in biodiesel and hydrogen fuel possibilities.
Nov 17, 2008

Planar MOSFET devices have been the back bone of the semiconductor industry for many decades now. Scaling has not only resulted in smaller and faster transistors. At the same time, single-gate MOSFET devices do not have adequate gate control over the channel resulting in degradation in the short-channel performance and leakage current of the scaled transistors.
Oct 16, 2008

Thanks to an agreement with Synopsys, the Electrical Engineering Department of the University of Chile has made available to its students the most modern university laboratory for integrated circuit design. The reactions from the students that have already used the Synopsys tools have been, “We couldn’t imagine that this was possible in Chile.”
Oct 16, 2008

Process induced transistor variability has emerged as an important issue in Nano CMOS technologies. For the sub-65nm technology nodes, variability aware device technology development and modeling thereof is the key to enable robust and manufacturable circuit designs.
Oct 16, 2008

Today’s Field Programmable Gate Arrays (FPGAs) are among the most adopted solutions for embedded systems implementations. Since their introduction in the mid ‘80s, FPGAs have provided new challenges to the existing VLSI design automation algorithms. FPGAs are no longer considered only as devices for prototyping, but they are also becoming companions to ASICs.
Oct 16, 2008

Effects of process-induced strain on the performance enhancement of Omega (O)-FinFETs have been investigated using Sentaurus process and device simulation tools. The capability of technology CAD (TCAD) for FinFET process development with strained silicon (strained-Si) as channel material is the main focus of our study.
Oct 16, 2008

Neural signal processing has many exciting applications today, including neuroscience research and neuroprosthetics. In such applications, spike sorting is a critical step in processing neural signals. Spike sorting has traditionally been performed in software. However, the growing demand for more recording channels and the need to transmit neural data wirelessly call for a hardware solution to perform spike sorting on-site and on-line.
Oct 16, 2008

IPL (Interoperable PCell Libraries) is an industry alliance, publicly announced in April 2007, to collaborate on the creation and distribution of open-source interoperable PCell libraries (IPL) that supports the OpenAccess database from the Silicon Integration Initiative (Si2). The five founding members of the IPL initiative are Applied Wave Research (AWR), Ciranova, Silicon Canvas, Silicon Navigator and Synopsys. Since then membership has grown to include Helic, JEDAT, Magma Design Automation and Virage Logic. Mentor Graphics and Pulsic are the supporting members. Each member has signed an agreement stating that they will support the interoperable PCell libraries as defined by the IPL initiative.
Oct 16, 2008