Researchers at SMU are in the forefront of research concerning Multiple-Valued Logic circuit design and EDA algorithms. Papers [1,2,3] cite the use of Synopsys VCS and SystemVerilog constructs that support the modeling and analysis of MVL circuits. The work in [4] cites the use of DesignCompiler, HSPICE, VCS, and PrimeTime for work in arithmetic circuit design for new architectures involving fixed-point squaring circuits. A new UML based synthesis approach for embedded system design is reported in [5] that uses SystemVerilog and associated Synopsys tools.
Aug 24, 2010

Simulation provides key insights into the physics of solar cell operation, enabling engineers to explore the full range of design alternatives. At the module and system levels, behavioral models allow engineers to examine design trade-offs that can affect system performance.
Jul 23, 2010

Multiband systems can flexibly create spectral holes to coexist with narrowband systems. Therefore, the multiband system with existing the narrowband system must be immediately detected to remove the interference on each system. We develop a channel estimator with a detection of narrowband interference system to implement multiband systems. The interfering system parameters, occupation of frequency band and angle-of-arrival, can detect before demodulation. The effective design and the detection error rate are evaluated via verification tests in anechoic chamber and computer simulations.
Jul 23, 2010

This paper analyzes the effectiveness of the use of thermal TSVs in lowering the overall average temperature of a 3D IC vertical stack as well as the impact and significance of thermal TSV count on the vertical and lateral thermal gradients in the stack for a given set of initial boundary conditions. A set of simulations were carried out using a 3DIC compact thermal model simulator on a multi-tier multi-die 3DIC design to access these effects of thermal TSVs.
May 17, 2010

Clock skew scheduling is a useful sequential circuit optimization method. The run time efficiency of this problem becomes crucial if it must be repeated iteratively in a higher level optimization. The widely recognized Burns' algorithm proposed to solve this problem suffers from high runtime complexity, which makes it unsuitable to be deployed in iterative optimization loops.
Apr 26, 2010

Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of design and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems.
Apr 26, 2010

With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively lower yields potentially undermine the profits of semiconductor companies across all industry segments. Embedding redundant logic into designs can improve product yields, but is this economically viable for most systems-on-chip?
Apr 26, 2010

This application note demonstrates the use of software tools in Synopsys Sentaurus TCAD suite, for the design and device simulation of a simple PN junction diode. It provides instructions on generating device structure, simulating the device, and visualizing the output, by using Sentaurus version 2008.09.
Dec 08, 2009

The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing problem with predefined connections between driver pads and bump pads. This problem has been shown to be much more difficult than the free assignment one, but is more popular in real world designs because the connections between driver pads and bump pads are typically predetermined by IC or packaging designers.
Nov 23, 2009

Faculty in the Electronics and ECE Departments at IIT Kharagpur extensively use Synopsys tools to facilitate a range of microelectronics and nanotechnology area research leading to more than 25 publications in journals and conference proceedings. Tools most often cited include Sentaurus, Medici, and Taurus. In this article we highlight the IIT Kharagpur TCAD activities which led to these publications.
Nov 23, 2009

This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers.
Oct 27, 2009

This paper describes Haydn, a hardware compilation approach which aims to combine the benefits of cycle accurate descriptions such as ease of control and performance, and the rapid development and design exploration facilities in behavioral synthesis tools.
Oct 27, 2009

We have developed a full-custom IC design flow based on Synopsys custom design tools and the recently released Synopsys 90nm generic library. The developed design flow can be used for teaching VLSI and digital IC design courses.
Aug 24, 2009

An open Educational Design Kit (EDK) which supports a 90nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PCells.
Aug 24, 2009

Researchers at IIT Bombay have used Synopsys tools to facilitate research in Nanoelectronics, leading to publications in reputed international journals and conferences in recent years. The following areas are under active investigation.
Aug 24, 2009

These papers focus on the research, development, and application of design techniques & methods, design processes, and EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits.
Jun 17, 2009

In this paper, we demonstrate that by applying SVD to the original Abbe’s kernels, the essential kernels according to their singular values can be efficiently extracted. The experimental results our algorithm, the Abbe-SVD method, shows over 100X of both runtime and memory saving over traditional Hopkin’s SVD methods for kernel generation.
Jun 17, 2009

Eighteen months ago, we started the analysis of a mathematical problem which was selected as the target application for the first fully automated ASIC development of the IIIE (Instituto de Investigaciones en Ingeniería Eléctrica).
Apr 10, 2009

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters.
Mar 30, 2009

The top student projects from the Special Topics in Circuits and Signal Processing course at the University of California Los Angeles are presented in this article. These projects used Synplify DSP tools in a Matlab/Simulink environment to model designs and perform architecture design. Students did a range of projects including theoretical studies of quantization effects in digital filters, optimization of finite word-length effects and parallel data processing for neuroscience.
Feb 26, 2009

Faculty in the Electrical Engineering Department at the University of Washington use several Synopsys tools for studies on reconfigurable systems. Design Compiler has been used to create hardware blocks. Pathmill has been used for extracting timing information, testing several layout generation methods and final analysis of the results.
Feb 26, 2009

Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a high-level model of the memory, greatly aids simulation-based validation, but accurate scoreboards are complex to create since often they depend not only on the memory and consistency model but also on its specific implementation. This paper describes a methodology of using a relaxed scoreboard, which greatly reduces the complexity of creating these memory models.
Jan 08, 2009

Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital signal processing to enhance the performance analog building blocks has become an active research topic. In this work, we present a digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution A/D converters.
Jan 08, 2009

Eighteen months ago, we started the analysis of a mathematical problem which was selected as the target application for the first fully automated ASIC development of the IIIE (Instituto de Investigaciones en Ingeniería Eléctrica). The PWL (Piece Wise Linear) Function Computation problem was chosen because this kind of function allows the representation of n-dimensional non-linear functions in a convenient way for computing systems, and non-linear functions are of relevance in control systems, one of the most active areas at the IIIE.
Jan 08, 2009