ARM, the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, and Synopsys, the technology leader for complex IC design, have teamed together for several years with R&D partnerships to address designers' leading-edge challenges for system-on-chip (SoC) design.
Low Power Design
- Low power verification experts from ARM, Renesas, and Synopsys, together with contributors from more than 30 companies, have collaborated to create the "Verification Methodology Manual for Low Power" (VMM-LP). Built on the widely adopted VMM methodology, VMM-LP includes a book as well as low power extensions to the VMM base classes and applications.
- In partnership, ARM and Synopsys have built on their extensive low power collaborative research and silicon technology demonstrators to create the Low Power Methodology Manual (LPMM) for SoC Design, published by Springer. The LPMM enables designers to adopt aggressive power management techniques.
- Focused on leakage management, the Synopsys-ARM Low power Technology (SALT) technology demonstrator SoC showed more than 96% leakage power savings.
- Concurrent with the launch of the LPMM, ARM and Synopsys announced an enhanced implementation Reference Methodology (iRM) incorporating the LPMM techniques for aggressive power management of the ARM1176JZF-S processor subsystem.
- The LPMM Chinese language edition was announced in a press release by Peking University Microprocessor Research and Development Center (MPRC) and Peking University Press.
- ARM and Synopsys formed an exclusive collaboration to deliver a low-power implementation solution for ARM's Intelligent Energy Manager™ (IEM) technology through the proven multi-voltage, multi-frequency Galaxy™ design flow.
- ARM recommends the jointly developed iRM for implementing ARM IEM-enabled cores, enabling easy adoption of this innovative system-level energy saving solution.
- The collaboration proved the IEM technology in SoCs manufactured at multiple foundries, demonstrating up to 65% energy savings.
- ARM, Renesas Technology and Synopsys have collaborated to define the industry’s first low power verification methodology. Planned for availability in the fall of 2008, it will be published in book form and also include free a SystemVerilog base class library (which builds on the VMM base classes) under an Apache 2.0 license. More information is available at www.vmmcentral.org.
Reference Methodologies
Libraries And Verification
- ARM's Artisan® Metro™, Advantage™ and Advantage-HS power-aware, multi-voltage libraries, as well as the Power Management Kit (PMK) for these libraries, were developed in close collaboration between the companies.
Synopsys DesignWare® Library includes synthesizable and verification components for AMBA™ 2 AHB/APB and AMBA 3 AXI interconnect. The coreAssembler tool is also included in DesignWare Library, automating the process of configuring, assembling, implementing and verifying an AMBA bus-based subsystems.
- ARM and Synopsys have jointly developed a reference verification methodology based on SystemVerilog and co-authoring the SystemVerilog Verification Methodology Manual - a "how-to" book on advanced verification techniques using SystemVerilog.
- A joint system-level design solution enables software development and verification of ARM processor-based SoCs.
- The Synopsys SVP Café directory provides a comprehensive list ARM Artisan physical IP (libraries) along with their support for Synopsys’ complete design flow.
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