ESP-CV is a tool designed to perform functional equivalence checks between two different design representations. The new power intent verification features in ESP-CV provide the ability to verify various types of power management circuitry used in low power designs. These designs may be described as Verilog behavioral models, RTL, gates, transistors, or a SPICE netlist.
Clay McDonald, R&D Manager, Implementation Group, Synopsys; Dave Hedges, CAE, Implementation Group, Synopsys
Sep 15, 2010

Increasing design complexity and the impact of new parasitic effects make accuracy and productivity for IC design and signoff analysis even more challenging beyond the 28nm process node. In this webinar, Synopsys experts will discuss how StarRC addresses these advanced challenges at 28nm through silicon-accurate modeling and high-performance extraction, enabling SoC designers to achieve signoff with increased confidence.
Krishnakumar Sundaresan, CAE, Synopsys
Sep 14, 2010

Learn how DesignWare® Data Converter IP blocks can be integrated to create a flexible interface that seamlessly communicates with any RF transceiver block without penalty in the total system power dissipation
Manuel Mota, Technical Marketing Manager, Converter IP Solutions Group, Synopsys
Sep 09, 2010

As the challenge of verification continues to grow, engineers are increasingly turning to verification planning, advanced coverage techniques and unique coverage technologies to optimize the tracking of verification progress and significantly improve the quality of their designs. In this webinar, you will learn about the latest advances in verification planning, coverage and coverage methodology. In addition, you will also discover some of the unique advantages of using VCS, including VCS’ Echo testbench coverage convergence technology.
Albert Chiang, Product Marketing Manager, Synopsys; Rahul Dani, R&D Engineer, Synopsys; Paul Graykowski Applications Engineer, Synopsys; Douglas Fisher Applications Consultant, Synopsys; and Jean Fong Applications Consultant, Synopsys
Sep 08, 2010

Learn how the Lynx Design System, including a production flow, the ability to pre-validate libraries and technology data, and project tracking and reporting features, helps control your design schedule!
Aditya Ramachandran, CAE, Synopsys; Neel Desai, Product Marketing Manager, Synopsys
Aug 25, 2010

Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.
Scott Wedge, Ph.D, Sr. Staff Engineer, Synopsys
Aug 18, 2010

Considering yield as one of the objectives during design has become a necessity at the 32/28nm node. In this webinar, you will learn techniques for addressing manufacturing during routing with IC Compiler’s Zroute technology which considers manufacturability as a routing objective.
Dr. Tong Gao, Synopsys Fellow, Synopsys; Yukti Rao, Product Marketing Manager, Synopsys
Aug 11, 2010

This technical webinar will explain how PrimeTime PX can be used to analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating. Attendees will learn how to further optimize their designs for power by analyzing which low-power techniques work best under differing conditions. You will also learn how to use PrimeTime PX to understand which modes of operation consume the most power.
David Le, Senior Manager, CAE, Implementation Group, Synopsys; Maria Tovey, Staff Engineer, CAE, Implementation Group, Synopsys
Aug 03, 2010

A complete review of TCAD simulation of power devices from the latest trends to future outlook, including silicon-based, SiC & GaN power devices. (Japanese/English)
Ricardo Borges, Sr. Manager, TCAD Product Marketing, Synopsys
Jul 30, 2010

In this webinar, come hear about the new IEEE specifications enabling Quality-of-Service and Energy Efficient Ethernet. You will also get an introduction to the DesignWare® Ethernet QoS and GMAC Universal MAC IP cores and how they can help you launch a new generation of networking products.
John Swanson, Senior Manager, Synopsys
Jul 29, 2010

Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.
Thomas Andersen, Director of R&D, IC Compiler, Synopsys; Mark Bollar, Director of Product Marketing, IC Compiler, Synopsys
Jul 28, 2010

This technical webinar will describe how easily you can access the embedded Rapid3D technology in StarRC Custom using existing interfaces and setup to drive high accuracy extraction for multiple design applications. Our experts will explain the latest field solver advancements in Rapid3D that deliver the high performance, capacity and near-linear multicore scalability, enabling you to apply the technology on designs consisting of tens to one hundreds of thousands of nets.
Omar Shah, Staff Engineer, CAE / Extraction, Synopsys
Jul 27, 2010

See how new Design Compiler 2010 technologies double the productivity of synthesis and P&R by enabling RTL designers to perform floorplan exploration while still in synthesis.
Sandra Ma, Sr. Director, Corporate Application Engineer, Alak Ghosh, Staff Corporate Application Engineer Webinar
Jul 22, 2010

This webinar focuses on optimization of rear point contact solar cells using 3-D TCAD simulation and addresses system-level simulation of PV arrays
Joanne Huang, TCAD R&D Engineer & Kurt Mueller, Saber Business Development Manager, Synopsys
Jul 22, 2010

Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.
Bradley Geden, Product Marketing Manager, Synopsys
Jul 21, 2010

This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010

NanoTime is the next-generation transistor-level static timing analysis solution that addresses the challenge of signal integrity (SI) analysis with custom designs. The advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins. Its seamless integration with Custom Designer provide users with additional productivity improvement such as configuration setup, timing reports with cross probing between schematic and layout and library model generation all within the Custom Designer environment.
Darryl Eng, Sr. CAE Manager, Implementation Group, Synopsys; Les Spruiell, Senior Manager, Product Marketing
Jul 15, 2010

This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality. Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.
Mitch Milner, R&D Group Director of Formal Verification
Jun 24, 2010

During this one-hour webinar we'll provide an overview of the LTE TDD mode and outline the mode frame structure and channel mapping differences between them. We'll also show how to utilize simulation models for TDD mode and explore corner cases outside the 3GPP spec.
Nils Tjernlund, R&D Engineer
Jun 23, 2010

Learn about IC Validator flows and features, including advanced layout parameter extraction with StarRC, interactive LVS Shortfinder and Blackbox LVS to enable faster design convergence.
Kerstin McKay, CAE Director, Synopsys
Jun 09, 2010

The next generation of the PCI Express® protocol, PCI Express 3.0, incorporates significant changes that go beyond the increase in link speed from 5 GT/s to 8 GT/s. In this webinar hear about the key specification changes for the PCI Express 3.0 protocol, equalization procedure, PIPE interface and electrical interface. In addition, learn about the trade-offs and practical implementation issues through examples and lessons learned from the development of Synopsys DesignWare IP for PCI Express 3.0. Finally, get a brief overview of the DesignWare® IP for PCI Express 3.0 solution.
Frank Kavanagh, Senior Engineering Manager
May 25, 2010

Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010

Successful, cost-effective verificaiton of a design requires quick and early bug detection. In this webinar, you will learn how Synopsys' Magellan hybrid technology speeds up bug hunting and provides unique value to design and verification teams.
Krishna Balachandran, Director of Marketing Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; Dan Benua, Principal Engineer, Synopsys
May 04, 2010

Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010