This technical webinar will explain how Galaxy Constraint Analyzer (GCA) helps improve designer productivity through look-ahead timing constraint analysis and debug technology tuned for the Synopsys Galaxy Implementation Platform. Attendees will learn how early feedback on constraint quality leads to more efficient runtimes and better quality of results in Synopsys’ Design Compiler® synthesis and IC Compiler physical implementation and PrimeTime timing signoff tools.
Savino Grillo, Manager, CAE, Synopsys Implementation Group, Synopsys; Lionel Corbet, Staff Engineer, CAE, Synopsys Implementation Group, Synopsys
Apr 07, 2010

Discover how FPGA-based rapid prototyping is used as a natural progression to complement emulation when the shortening of development time is critical to the overall success of ASIC and SoC projects.
Neil Songcuan, Synopsys
Mar 31, 2010

Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.
Bradley Geden, Product Marketing Manager, Synopsys; Tom Hsieh, AMS CAE, Synopsys
Mar 25, 2010

This webinar covers the following: early incremental power network fix guidance within ICC based on PrimeRail’s rail checking capability, PrimeRail’s inrush analysis capability for switch architecture control design during the IC Compiler design planning phase, and finally an ECO placement link after routing using PrimeRail’s decoupling capacitance analysis and insertion.
Li-Pen Yuan, Group Director, R&D, Implementation Group
Mar 24, 2010

SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.
Marc Swinnen, Sr. Product Marketing Manager, Synopsys; Christopher Shaw, Technical Marketing Manager, Synopsys
Mar 23, 2010

Whether you are using FPGAs to verify your ASIC or as a final implementation platform, this webinar will illustrate techniques to help you speed up your synthesis iterations by a factor of 2 vs. traditional approaches, and achieve up to 2 times the turnaround time from RTL to board with better results stability from one run to the next. Techniques for more efficient debug and optional team design techniques are also covered.
Angela Sutton, Synopsys
Mar 03, 2010

First in a series addressing 32/28nm sign-off bottleneck challenges and the solutions best suited to mitigate these challenges. Learn how Synopsys’ In-Design solutions make it possible for place-and-route engineers to accelerate design closure by enabling signoff analysis from within the implementation flow.
Dan Page, Vice President of R&D, Implementation Group, Synopsys
Mar 02, 2010

The latest algorithms and best practices for 3-D TCAD simulation to derive maximum benefit from the comprehensive 3-D capabilities in Sentaurus TCAD.
Sudarshan Krishnamoorthy, Technical Marketing Manager, Synopsys; Simeon Simeonov, Ph.D., R&D Manager, Synopsys
Feb 24, 2010

How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.
Uyen Tran, Director CAE, Synopsys; Norb Heindl, Senior Staff Engineer, CAE, Synopsys
Feb 17, 2010

This webinar details the flexible on-chip bus architecture of the DesignWare interconnect fabric that enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design to deliver maximum bandwidth while reducing area, routing congestion and power.
Fred Roberts, Corporate Applications Engineer, Synopsys
Feb 10, 2010

In this webinar, you will learn about the basics of transaction-level modeling, why it is needed, how it integrates with an RTL design and how the Synopsys VCS functional verification solution supports both transaction-level and pin-level debug in its Discovery Visualization Environment (DVE).
Albert Chiang, Product Marketing Manager, Synopsys; Yasser Khan, Sr. Corporate Applications Engineer, Synopsys; Dr. Bassam Tabbara, Senior Staff R&D Engineer, Synopsys; Brett Kobernat, Applications Consultant, Synopsys
Jan 27, 2010

A joint presentation featuring Synopsys and TSMC addressing 32/28nm design challenges and the solutions available in IC Compiler and the Galaxy Implementation Platform from both the EDA vendor and foundry perspectives.
Marco Casale-Rossi, Product Marketing Manager, Synopsys; Tom Quan, Deputy Director, DMSM DTP, TSMC; Ashwini Mulgaonkar, Marketing Director, Synopsys
Jan 26, 2010

A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Synopsys; Troy Epperly, Corporate Applications Engineer, Synopsys
Jan 20, 2010

Learn how to use the Synphony high-level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink.
Chris Eddington, Director of Product Marketing, Synopsys; Josefina Hobbs, Technical Solutions Architect, Synopsys
Jan 19, 2010

This webinar highlights memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 15, 2009

This webinar discusses the application of TCAD to high-k/metal-gate transistors and 3-D modeling FinFET devices, focusing on the physical models and 3-D modeling techniques required to achieve successful simulations.
Synopsys
Dec 01, 2009

Learn how StarRC Custom enables high accuracy and optimized extraction for improved simulation throughput. Demonstrations include a 3-D field solver, context-specific MOS device parasitic extraction, CustomSim simulation efficiency links and OpenAccess-based integration with Custom Designer.
Baribrata Biswas, Group Director, R&D / Extraction , Synopsys; Omar Shah, CAE / Extraction, Synopsys
Nov 11, 2009

Learn all about constraints and how their proper specification and use will help you quickly achieve your verification goals. Synopsys’ Magellan hybrid formal tool helps detect and debug over-constraining of your formal setup, thereby increasing your confidence in your formal verification results.
Krishna Balachandran, Director of Marketing, Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; and Dan Benua, Principal Engineer, Synopsys
Nov 11, 2009

Automotive ICs and systems pose number of key problems; harsh operating conditions, increasingly complex HW/SW interaction, and manufacturability of IC designs. Learn how Synopsys' "Software to Silicon Methodology" helps you analyze, design, and verify designs for the highest-quality results.
Anthony Stone, Synopsys
Nov 10, 2009

Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, Synopsys; Fredrik Ivarsson, Custom Design Corporate Applications Engineer, Synopsys
Nov 05, 2009

Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, Synopsys; Chris Shaw, Technical Marketing Manager, Synopsys
Nov 03, 2009

There is a thriving ecosystem around IC Compiler and the Galaxy Implementation Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity.
JC Lin, Synopsys
Oct 31, 2009

This webinar discusses how the unique features of Altera's high-end Stratix-FPGAs combined with Synopsys high-performance rapid protoyping solutions enable new use modes and capabilities for algorithmic acceleration, as well as for highest performance rapid prototyping.
Synopsys
Oct 29, 2009

Learn how VCS multicore technology allows users to reduce verification time for long-running tests by leveraging their multicore computing infrastructure. We cover VCS multicore technology’s two flexible use models: application-level parallelism (ALP) and design-level parallelism (DLP).
Chiang, Product Marketing Manager, Synopsys; Usha Gaira, Corporate Applications Engineer, Synopsys; Amitabh Chand, Corporate Applications Engineering Manager, Synopsys; and Jatinder Goraya, Research and Development Engineer, Synopsys
Oct 27, 2009